05:16 <Garfias> How can I create a standalone LiteSDRAM core? I have the DE10-Lite with IS42S16320F, I see that it is in the modules list, but I do not understand from the examples how a standalone core (w/o cpu) can be created

09:38 <davebee> I want to be able to use interrupts with the liteeth Ethernet interface. I have found the Linux driver, but what support is there for OS-less systems? What is the best way of building a small footprint system that can use interrupts?

09:55 <_florent_> Garfias: LiteDRAM has a standalone generator: https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py it can be use to generate standalone cores from .yml files and litedram_gen command

10:14 <_florent_> davebee: The BIOS uses interrupt for some peripherals, but I'm not sure to remember if Ethernet uses it. If not, you could have a look at the UART interrupt support.

10:17 <davebee> _florent_: thanks. I have uart/timer/eth interrupt hardware. I need to get a system tick working, so I'll look at the uart code and get a timer tick working. Then look at eth.

10:17 <_florent_> davebee: good

13:43 <davebee> There is a problem using the timer0 as a system tick. It is used in the busy_wait(ms) and busy_wait_us() functions, which overwrite the regs. These functions are used internally by the sdcard, sata etc. drivers.

13:59 <davebee> Is there a way to add a second timer, ie timer1 ?

15:48 <_florent_> davebee: It should be possible with add_timer: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1026-L1031

15:55 <davebee> _florent_: Thanks. Getting ETHMAC interrupts. Not sure I'm up to writing a driver for it though. It is currently dropping Tx packets, in polled mode.