_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> tnt: When you have time (no hurry), I would be interested by a test of the PCIe Gen3 X8 on your config. Just update LiteX/LitePCIe and make sure to upload the updated driver to the remote machine with the board (Since I added a soft reset of the SoC during the litepcie_probe).
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<_florent_> tnt: The issue is fixed on the machine I was looking at (The main issue was that the 100MHz PCIe input clock was not properly constraint in client's design), but I did other improvements while looking at this so I hope it will fix the issue on your system. If not, I could share code to add LiteScope on useful signals to see what is going on.
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<tnt> _florent_: Ack. I'll make a build and check it tonight.
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