_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
bl0x has quit [Ping timeout: 240 seconds]
bl0x has joined #litex
Degi_ has joined #litex
Degi has quit [Ping timeout: 268 seconds]
Degi_ is now known as Degi
ewen has joined #litex
ewen has quit [Ping timeout: 240 seconds]
<tnt> _florent_: you were using data_width=256 for x8 right ?
<_florent_> tnt: yes
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<_florent_> the other difference is the machine (I'm testing on a H270M-PLUS motherboard with an I9), but since X4 is working, I would have expected X8 to also work on your machine
<tnt> Ok, I'll give that a shot with sys_clk at 200M and might try to regenerate the .xci in case I screwed it up the first time around.
<tnt> _florent_: is the fpga on that board faster than a zu11eg-1 ? At sys_clk 200M, I get min-pulse-width violation for the clk_4x for the DDR4.
<tnt> (damn, yeah, answering my own question the 1525 board has a -2l speedgrade vs -1 speedgrade of the zu11eg)
C-Man has quit [Ping timeout: 250 seconds]
_franck_ has quit [Ping timeout: 256 seconds]
_franck_ has joined #litex
C-Man has joined #litex
<acathla> If I have two or more memories (Flash) on the same SPI bus, with a different CS_n signal, how can I map that to the wishbone bus? Is it something LiteSPI can do?
<acathla> I could self.bus.add_slave to two different regions but to the same bus, but I'm not sure how to know which region is accessed, unless I use static addresses.
<tnt> acathla: doesn't look like it's supported.
<acathla> That's what I thought :/
<acathla> I try with the static address first
_whitelogger has joined #litex
somlo_ has joined #litex
somlo has quit [Remote host closed the connection]
ilia__s0 has joined #litex
ilia__s has quit [Ping timeout: 272 seconds]
ilia__s has joined #litex
ilia__s0 has quit [Ping timeout: 245 seconds]
ilia__s5 has joined #litex
ilia__s has quit [Ping timeout: 250 seconds]
ilia__s5 is now known as ilia__s