_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tcal> Is there already a generic delta-sigma DAC LiteX core? Maybe there's so many variations about how to do the buffering that everyone just rolls their own? I made a simple one with no buffering, just a CSR to hold the current value -- it's just a few lines of Migen. With this simple core, software is responsible for correct timing/synchronization of the samples.
<tnt> Mmmm, the way the DMA works in prog mode is actually pretty annoying :/
<_florent_> tnt: The DMA is only covering the use cases I needed, but it should not be too complicated to change the high level behavior.
<tnt> Yeah, working on it. I was hoping to use the HW as-is and only change the sw, but the loop status is not suitable for what I needed so I had to tweak it.
<tnt> I got a single buffer write/read cycle working. Now further tweaking the kernel driver ...
<tnt> I might end up just substituting the LitePCIeDMAScatterGather with a more custom one. It'll depend if all the CSR writes to refill the descriptors end up being a slow down or not.
<tnt> (i.e. like instead of having to rewrite each descriptors individually, I'd add a single CSR and if you write 50 to it, it auto-resubmits 50 descriptors with a single CSR write)
<_florent_> I also probably did the initial code in 2014, so would probably do it differently now, but now that things are used, I avoid changing things too much, but different DMAs could eventually be implemented.