_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tnt> _florent_: btw, did you get a chance to look at pcie 8x ?
<tnt> Also, I'd like to get the GTH ultrascale support for liteiclink upstreamed.
<_florent_> tnt: Sorry, not yet, but I'm starting a build with PCIe 8X on the FK33 right now
<_florent_> tnt: Sure for GTH Ultrascale support to LiteICLink (and thanks), can you create a PR? I could then figure out the best way to integrate (duplication of code vs simplicity to copy wizard generated parameters)
<_florent_> tnt: where you also planning to upstream the tool you created to get parameters from the wizard? (it could help switching to the non-duplicated GTH wrappers)
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<tnt> _florent_: Huh, I can send it to you, but it's not exactly a user-friendly / ready-to-use thing ... you have to generate all the files manually and cut-and-paste the section with the params into a .txt files
<tnt> you can have a look.
<tnt> (see like gthe4_channel_wiz_wrapped.txt for instance, it has a comment line at the top where I cut&pasted it from)
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<_florent_> ok thanks, I see
<_florent_> thanks also for the PR, I'll try to have a closer look at it soon
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<tnt> Mmm ... so I think my issue is in the clock crossing between the PHY RX domain and the JESD domain. Data right out of the phy ( before the LiteJESD204BRXCDC ) seems good. Data after it is not.
<tnt> (for context ... trying to bring up jesd link ... I could swear I got it up in early tests back end of december but I have been unable to do it again since)
<tnt> Ok, nm ... I had clocking setup wrong. Last week during the debug I had switched a divider and forgot to put it back. Not sure what was the problem I had earlier, but it got fixed apparently. Now links get to the DATA phase. Now I "just" need to figure out how to properly synchronize multiple chips.
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