04:45 <trabucayre> tnt: no. But I can check datasheets

05:59 <tnt> trabucayre: I randomly just added it pretending it was a kintex 7 and it seemed to have worked just fine.

06:00 <tnt> _florent_: and forget what I said about hold violations, I was dumbly looking at _timing_synth.rpt instead of _timing.rpt ... doh ....

06:06 <trabucayre> tnt: xilinx is quite coherent: all devices works with the same programming sequence :)

06:07 <trabucayre> If you have devices to add ...

08:47 <tnt> trabucayre: PR opened :)

11:04 <davebee> I'm trying to integrate some Amaranth into Litex. I have the Verilog generation working. I've written a function to build a Python migen stub with a Module to wrap the Instance and add the Verilog source. I've built a simple free running counter and it works fine. I want to be able to connect the wishbone bus of the CPU generated by Litex to my

11:04 <davebee> Amaranth component. I don't know where the bus signals are in Litex. Where should I be looking?

14:02 <_florent_> davebee: Hi, you can have a look at: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/usb_ohci.py

14:03 <_florent_> davebee: You can create a wrapper around your generated Amaranth core exposing a Wishbone interface:

14:03 <_florent_> https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/usb_ohci.py#L26

14:03 <_florent_> then create your instance/connections: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/usb_ohci.py#L38-L78

14:04 <_florent_> add the generated sources: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/usb_ohci.py#L108

14:05 <davebee> Great. Thanks. I'll take a look at that. I've got everything else running - so I'm running a mix of Amaranth, VHDL and migen/Litex, but not connected together yet.

14:05 <_florent_> and finally integrate this wrapper module in the LiteX SoC, ex: https://github.com/enjoy-digital/litex_vexriscv_smp_usb_host_test/blob/master/digilent_arty.py#L149-L150

14:06 <davebee> I was fiddling with add_slave() and SoCRegion() but couldn't work it out. Many thanks.#

15:43 <_florent_> tnt: I've improved the reset of the CDC modules used in LitePCIe PHY and this fixed the dma_hanging I was seeing on a design. It also seems to have fixed the Decklink behaviour since I'm now able to get PCIe + DRAM working simultaneously.

15:43 <_florent_> tnt: I'm doing more tests, but that's also possible it fixed https://github.com/enjoy-digital/litepcie/issues/90

17:01 <tnt> _florent_: oh, very interesting. I'll test that on the declink since I'm preparing now and then on the ADI board.

17:31 <_florent_> tnt: great, thanks

18:36 <tnt> _florent_: decklink with ram indeeds seems to work now.

18:36 <tnt> I'm still having trouble getting uart to work on it, but might be a physical issue / cable thing. I need to check that.

19:17 <_florent_> tnt: Good for the ram. For the UART, I just probed the pins, I haven't tested them as UART.

19:18 <_florent_> tnt: BTW, if you have time for a build, I would be interesting to know if the two other DRAM modules have been reversed correctly:

19:18 <_florent_> tnt: here: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/decklink_quad_hdmi_recorder.py#L79

19:19 <_florent_> tnt: changing to 4, 5, 6, 7 would use the two other DRAM modules

19:39 <tnt> _florent_: sure, I can give that a shot. Need to find a way to see the memtest results :p

20:01 <tnt> _florent_: the other ram banks works fine.

20:24 <_florent_> tnt: did you managed to get the UART working? :)

20:24 <tnt> _florent_: yes.

20:24 <_florent_> tnt: ah good, what was the issue?

20:25 <_florent_> tnt: Thanks for the ram test, nice to know this is also working

20:25 <tnt> _florent_: tbh, I have no idea what I screwed up the first time around. I disconnected everything and plugged in the scope to see what was wrong ... and everything looked fine. I reconnect the usb-serial cable ... and it works.

20:26 <tnt> And now I also got uartbone working at 2M baud so it's all fine.

20:26 <_florent_> BTW, when generating the design with PCIe (and with Crossover UART), you can just also load the Linux driver and do get the console on /dev/LXU0

20:28 <tnt> yeah, I saw that. But since I wanted to use the bridge to debug dma peripheral, I figured avoiding going through pcie is probably a good idea :p

20:29 <tnt> I'm rebuilding an ADI board bitstream with x8 pcie, we'll see if the fix you made helped with that too.

20:51 <tnt> _florent_: btw, ever tried having 2 litepcie devices in the same system ?

20:51 <tnt> [13858.278069] sysfs: cannot create duplicate filename '/devices/platform/liteuart'

20:53 <_florent_> tnt: yes, but probably not with the LiteUART driver

20:58 <tnt> _florent_: at first glance it didn't seem to have solved my x8 issues :/

20:58 <tnt> only litepcie needed updating right ?

21:07 <_florent_> litex too