_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<amstan> is there a cool dev board that has USBC/Thunderbold/PCIe on it?
<amstan> so i could unify it with my computer's memory
<CarlFK> _florent_: https://github.com/timvideos/litex-buildenv/blob/master/Makefile#L170 MAKE_CMD=\ $(PYTHON) -u ./make.py \
<CarlFK> --platform=$(PLATFORM) \ --target=$(TARGET) \ ...
<CarlFK> given the $params any guess as to what might work?
<CarlFK> guess = dont' spend much time as I may be the only person that uses this to verify the parts still work
<CarlFK> just because something stops working does not mean it needs to be fixed
<CarlFK> mithro: is there any point to fixing the old one?
<mithro> CarlFK: Not really, unsure if the new version is worth fixing as LiteX BuildEnv should be retired sometime....
<mithro> https://github.com/litex-hub/linux-on-litex-vexriscv is a pretty good replacement for the Linux stuff
<CarlFK> the new version has the same error
<mithro> Log a bug and someone from Antmicro might take the time to fix, but don't count on it
<mithro> @CarlFK Feel free to add a "me too" and a log which is easily searchable?
<CarlFK> k
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<cr1901> _florent_: Are any of the current cores in litex written in Amaranth?
<cr1901> (Under the soc/cores directory. I know minerva CPU is amaranth)
* cr1901 misses when he knew LiteX enough that he could create a SoC in an hour lol
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<tnt> Any clue what would cause the pcie core to go to Polling.Compliance ?
<tnt> to give a little of context: this happens when loading a new bitstream when the machine is already booted and only if the machine was booted with a bitstream already loaded. Also if I reboot the PC, then the core will sync just fine (i.e. leave Compliance and go through training).
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<_florent_> cr1901: in litex directory, there is only Minerva for now. It could also be interesting to reuse properly integrate Luna in the future
<_florent_> tnt: sorry I saw your interesting results in the issue but haven't been able to have a closer look yet
<tnt> TBH after the change I made I think the issue might be in the BIOS or ACPI tables.
<_florent_> tnt: Regarding the filtering of the Clk with the reset, I added it on 7-series since was required on a custom hardware, but we should maybe make it optional
<tnt> When the PC boots without cards, the bios doesn't init anything and I have to do it myself, that's fine. But I guess when it detects a cards, it must start some monitoring process or something and when the link is lost it doesn't restart properly.
<tnt> _florent_: What I was thinking was to possibly add a small reset counter block so that when the external reset is released, it re-enables the clock but keeps the internal reset asserted for a bit longer.
<tnt> Although TBH ATM the way it works is "good enough" for my application, it's mostly a curiosity as to why it doesn't behave.
<tnt> What's a bit more annoying is that x8 doesn't work.
<_florent_> tnt: Sorry I'm not sure to remember or find the behavior in the issue with x8? The board is not seen at all with lspci?
<tnt> it enumerates fine and --ident works fine. But dma test just hangs.
<tnt> I'll re-check tomorrow, and open a new issue about it with the tests / behaviors I observe.
<_florent_> ok, if you can also share the pcie_usp_support, I'll have a look
<tnt> What do you mean ? I use the pcie_usp_support.v is in the litepcie repo.
<tnt> Or did you mean the .xci ?
<_florent_> tnt: I need to have a look but the adaptation of pcie_usp_support is probably different between the x4 and x8
<tnt> yes it is.
<tnt> But there is a x8 version in the repo. I didn't write it.
<_florent_> ok that's good then. I'll do some verification in the one present in the repository
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