04:58 <amstan> is there a cool dev board that has USBC/Thunderbold/PCIe on it?

04:59 <amstan> so i could unify it with my computer's memory

05:36 <CarlFK> _florent_: https://github.com/timvideos/litex-buildenv/blob/master/Makefile#L170 MAKE_CMD=\ $(PYTHON) -u ./make.py \

05:36 <CarlFK> --platform=$(PLATFORM) \ --target=$(TARGET) \ ...

05:37 <CarlFK> given the $params any guess as to what might work?

05:38 <CarlFK> guess = dont' spend much time as I may be the only person that uses this to verify the parts still work

05:38 <CarlFK> just because something stops working does not mean it needs to be fixed

05:40 <mithro> @CarlFK The newer version of that tutorial is https://github.com/timvideos/litex-buildenv/wiki/HowTo-LCA2018-FPGA-Miniconf-VexRiscv-Renode

06:25 <CarlFK> mithro: is there any point to fixing the old one?

06:41 <mithro> CarlFK: Not really, unsure if the new version is worth fixing as LiteX BuildEnv should be retired sometime....

06:41 <mithro> https://github.com/litex-hub/linux-on-litex-vexriscv is a pretty good replacement for the Linux stuff

06:43 <CarlFK> the new version has the same error

06:43 <mithro> Log a bug and someone from Antmicro might take the time to fix, but don't count on it

06:50 <CarlFK> https://github.com/timvideos/litex-buildenv/issues/751

06:51 <mithro> @CarlFK Feel free to add a "me too" and a log which is easily searchable?

06:51 <CarlFK> k

16:37 <cr1901> _florent_: Are any of the current cores in litex written in Amaranth?

16:37 <cr1901> (Under the soc/cores directory. I know minerva CPU is amaranth)

20:01 <tnt> Any clue what would cause the pcie core to go to Polling.Compliance ?

20:03 <tnt> to give a little of context: this happens when loading a new bitstream when the machine is already booted and only if the machine was booted with a bitstream already loaded. Also if I reboot the PC, then the core will sync just fine (i.e. leave Compliance and go through training).

20:24 <_florent_> cr1901: in litex directory, there is only Minerva for now. It could also be interesting to reuse properly integrate Luna in the future

20:27 <_florent_> tnt: sorry I saw your interesting results in the issue but haven't been able to have a closer look yet

20:28 <tnt> TBH after the change I made I think the issue might be in the BIOS or ACPI tables.

20:29 <_florent_> tnt: Regarding the filtering of the Clk with the reset, I added it on 7-series since was required on a custom hardware, but we should maybe make it optional

20:30 <tnt> When the PC boots without cards, the bios doesn't init anything and I have to do it myself, that's fine. But I guess when it detects a cards, it must start some monitoring process or something and when the link is lost it doesn't restart properly.

20:31 <tnt> _florent_: What I was thinking was to possibly add a small reset counter block so that when the external reset is released, it re-enables the clock but keeps the internal reset asserted for a bit longer.

20:32 <tnt> Although TBH ATM the way it works is "good enough" for my application, it's mostly a curiosity as to why it doesn't behave.

20:33 <tnt> What's a bit more annoying is that x8 doesn't work.

20:35 <_florent_> tnt: Sorry I'm not sure to remember or find the behavior in the issue with x8? The board is not seen at all with lspci?

20:37 <tnt> it enumerates fine and --ident works fine. But dma test just hangs.

20:37 <tnt> I'll re-check tomorrow, and open a new issue about it with the tests / behaviors I observe.

20:43 <_florent_> ok, if you can also share the pcie_usp_support, I'll have a look

20:50 <tnt> What do you mean ? I use the pcie_usp_support.v is in the litepcie repo.

20:51 <tnt> Or did you mean the .xci ?

21:02 <_florent_> tnt: I need to have a look but the adaptation of pcie_usp_support is probably different between the x4 and x8

21:04 <tnt> yes it is.

21:04 <tnt> But there is a x8 version in the repo. I didn't write it.

21:28 <_florent_> ok that's good then. I'll do some verification in the one present in the repository