<tpb>
Title: API reference — Migen 0.8.dev0 documentation (at m-labs.hk)
<_florent_>
tnt: Reset is synchronous with Migen, to write an async reset, you have to do it in Verilog and an instance or use a Xilinx primitive directly
<tnt>
_florent_: tx for confirming what I suspected.
<zyp>
can't you just make a small clock domain for interacting with the particular signal and use an AsyncResetSynchronizer to drive the reset of the domain?
<tnt>
The goal of the reset async in this case would be to ensure reset works (i.e. output signal goes to defined state) when the clokc isn't running.
<cr1901>
This is one of the things amaranth fixes, which has async_reset=True param for Signals
<cr1901>
And indeed, helpful for resets w/o a clock (where only async resets work)
<tnt>
Yeah, the orange crab analog part is a copy of what I did on the icepick.
<cr1901>
tnt: Thanks, I've been on a bit of an ADC kick lately... hope it ends soon, b/c reading about them for too long makes my head hurt :D
<tnt>
lol. I'm not claiming that ADC method is any good btw, but it worked good enough for me. You could also do sigma-delta with the same external hw but I didn't want a high frequency toggling node. A 'single conversion' kind of thing was more what I needed.
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<cr1901>
I wanted an interrupt that automatically lets you know when a measurement is done, but that's like 5 lines of code for a LiteX core
<cr1901>
Otherwise, single conversion is fine
<tnt>
_florent_: So I'm faced with the classic "vivado analyzes path it shouldn't" between pcie domain and sys_clk domain.
<tnt>
If I do : platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) it doesn't help.
<tnt>
If I do : platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets pcie_clk]] -asynchronous")
<tnt>
then that last one works. The resulting .xdc is the same but the second also has that line in the `.tcl`
<_florent_>
tnt: it could be related to the fact that synthesis of the PCIe PHY/LiteX design are done separately and previous constraint is ignored by Vivado. It's indeed sometimes painful to have false paths applied correctly
<_florent_>
tnt: that's also some cases where LiteX does not necessarily simplify things with the extra-layers
<tnt>
mmm. But the IP are done both before the read_xdc and before the "# Add pre-placement commands" where that also ends up.
<tnt>
I guess the [get_clock / get_net ...] might not work because that done before synthesis so those don't exist yet ?
<cr1901>
err sense_cnt by 2*. It's an edge detector (pos/neg edge of inpt clock), but I don't see why you need to incr by 2 once you've reached the comparator transistion
<tnt>
it increments by 1 or 2 depending on which bits are sampled at 1.
<tnt>
The thing (at least in the ice40), at the transition point, it tends to sometime sample a 1, sometimes a 0 and you get a more precise result by counting all the 0 (or all the 1) over a fixed interval rather than measuring the cycles it takes to get to the first one or first zero.
<cr1901>
Oh wait... concat in Verilog is {bit1, bit0} if your signal is declared [1:0] isn't it?
<cr1901>
Okay, this makes sense, I mixed up the concatenation order
<cr1901>
Effectively, you're using both of input_clk's edges to the SB_IO to double the resolution/number of measurements taken
<tnt>
cr1901: precisely.
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