_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tnt> _florent_: Morning.
<tnt> _florent_: Did you ever investigate the UART Rx/Tx lines on the quad recorder ?
<tnt> They're not in the platform file but there is clearly a marked uart connector. Not sure if it's connected to the fpga though.
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<_florent_> tnt: Hi, I think I only investigated the debug pins, not the UART ones
<_florent_> tnt: But I could give it a try if this could be useful for you
<_florent_> tnt: Otherwise, on the quad recorder, I'm not sure I got LitePCIe working yet with it. It should not be far and the PCIe lanes should be fine, but last time I tried I think the PCIe was not enumerated correctly.
<_florent_> tnt: This could be related to the issue you saw in the last week or a wrong reset signal
<_florent_> tnt: Happy to put more effort on this if you are also playing with it.
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<tnt> _florent_: I ordered a card yesterday. Not really for me, it's just to have a platform with litepcie I can ship to someone helping me on the software/kernel side that's hopefully close enough to the real target hardware (which is both expensive and hard to find ATM so I can't just ship them one of those boards).
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<tnt> _florent_: :)
<tnt> Are they level translated to 3v3 or are them 1v5 ?
<_florent_> it's translated to 3.3v
<tnt> Oh is the DDR what you unsoldered or did they reduce it to 1 bank ? (I was just using reference pics from https://www.thomann.de/be/blackmagic_design_decklink_quad_hdmi_recorder.htm )
<tpb> Title: Blackmagic Design DeckLink Quad HDMI Recorder – Thomann België (at www.thomann.de)
<tnt> nice to see what's under the heatsink. Looks like just a flash and the clock gen maybe ?
<_florent_> tnt: In fact I originally desoldered the 4 DDR for probing
<_florent_> tnt: I then reballed 2 and resoldered them and got LiteDRAM working on these 2
<_florent_> tnt: but I damaged on DDR module, so need to order a few to resolder them
<_florent_> but for my current tests, I already have enough bandwidth with the 2 modules
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<tnt> _florent_: I haven't looked yet, but how fast has litedram been tested with for DDR3 / DDR4 ?
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<_florent_> tnt: On a Kintex7, I did this overclocking test last year: https://twitter.com/enjoy_digital/status/1357628386634575873
<_florent_> tnt: the DDR3 was rated for 1600MT/s
<_florent_> tnt: On DDR4/Ultrascale, I'm also using it on client's designs at up to 1400-1600MT/s too
<tnt> Ok nice. I'll have a go at 250 MHz sysclk see if that works on the usp+ ddr4.
<tnt> It'd just fit nicely with the samplerate of 245.76Msps.
<_florent_> IIRC the limiting factor is the max bufg frequency currently (but the DRC can be disabled for tests)
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<tnt> If it's an issue, it's not the end of the world, I just like to keep things synchronous when I can and having all the DSP run at 1 sample per cycle is just more convenient.
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<_florent_> tnt: I just re-tested the PCIe on the HDMI Quad Recorder
<_florent_> tnt: and it seems to work fine
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
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<tnt> _florent_: awesome thanks !
<tnt> i'm hoping to receive mine before the weekend ...
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<_florent_> tnt: back from lunch, I just also tested the DMA and it's also working
<_florent_> tnt: but it seems the link was downgraded to 1X instead of 4X, I'll have a look
<_florent_> tnt: otherwise, you might find this useful if you use LiteScope to debug your design: https://twitter.com/enjoy_digital/status/1504126670156046345
<_florent_> it's just a quick PoC for now, but can already be more convenient than the command line
<_florent_> tnt: When changing the PCIe slot, the card is now correctly recognized as X4, so maybe it was just not correctly inserted.
<acathla> https://github.com/litex-hub/litespi/blob/master/litespi/core/mmap.py#L169-L170 those two lines seem useless. And it frees 4 LC on an ice40 \o/
<tnt> _florent_: some physical slots are physical x4 and only wired for x1 ... what mother board is it ?
<tnt> _florent_: board itself is x8 also not x4 :p
<tnt> _florent_: I'll give the litescope cli a try next time I need to use it. ATM I run the capture on a remote host and scp the vcd to mylaptop.
<_florent_> tnt: Indeed, forgot the board was x8, while it's still in the computer, let's do a test!
<_florent_> tnt: BTW, it's also possible to only run litex_server on the remote host and litex_cli/litescope_cli on your local machine
<tnt> _florent_: yeah, I know but I usually find the added latency hurts performance. Although now that there is long bursting, I should retry that since it might have lessened the impact of wifi latency quite a bit.
<_florent_> It's possible but I don't use this very often, only for some specific use-cases
<tnt> Damnit, just spend like 30 min trying to debug i2c accesses and why it was not working ... to realize I got the i2c pin assignement wrong in the platform ... confused bank 64 and bank 67 on the schematic.
<cr1901> It happens :)
<_florent_> Arf...
<tnt> Yeah, I got confused because I had just modified my i2c controller so a single controller could control multiple physical bus/pins-pairs and so naturally I thought I had screwed that part up, not the actual pin assignement.
<tnt> _florent_: btw have you seen this https://libre-soc.org/docs/gtkwave_tutorial/ ?
<tpb> Title: gtkwave tutorial (at libre-soc.org)
<tnt> Generating gtkw from litescope directly with better hierarchical names and fsm state names and such would be pretty cool :)
<acathla> Oh, colors!
<_florent_> tnt: in fact we should first add hierachy to the generated verilog (it should be possible by keep Migen for now and revisiting the final verilog generation steps)
<_florent_> tnt: but yes, adding colors to LiteScope would be good
<_florent_> tnt: we also have some code that is used by litex_sim: https://github.com/enjoy-digital/litex/blob/master/litex/build/sim/gtkwave.py
<_florent_> acathla: Thanks, I'll have a look at the LiteSPI changes you suggest
<_florent_> tnt: PCIe 8X is also working on the decklink quad hdmi recorder
<tnt> _florent_: Ok great. I'll need to test that here, it'll be interesting if it works here. (still not working on the adi board for some reason even after regenerating the .xci and sys_clk 200M, but I haven't dug further for now).
<_florent_> tnt: but just for info, there still seems to be an issue when enabling both DRAM and PCIe on this board: when enabling DRAM, the board is enumerared with lspci, but accesses do not work.
<_florent_> tnt: so when testing PCIe, maybe first disable DRAM with --integrated-main-ram-size=0x100
<tnt> Oh, that's weird.
<_florent_> tnt: I'll try to investigate, but just wanted to share this with you to avoid loosing time
<tnt> _florent_: yup thanks.
<_florent_> tnt: I think that's the reason why PCIe was not working when I was tested it in the past
<_florent_> Thanks @acathla, the changes make sense and are integrated with https://github.com/litex-hub/litespi/commit/7d32810ee05eb96e5cf4152483a3e1e501f9113c
<jevinskie[m]> <_florent_> "tnt: in fact we should first add..." <- _florent_ verilog hierarchy!? Be still my heart, that is my biggest peeve with migen that amaranth solves. Would be great for waveform viewing as mentioned but also for design viewing in Quartus/Vivado and resource usage breakdown
<acathla> _florent_, thanks! That's a major improvement =)
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<tnt> Is there a way to specify a default pullup in the platform file ?
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<tnt> nm, got it. Misc("PULLUP") works.
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<_florent_> jevinskie[m]: It's becoming limiting yes to not have the hierarchy. I already reworked/replaced the final verilog generation a few weeks ago and would like to go continue and go further to have the hierachy (at least optionally).
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<SpaceCoaster> What is the hierarchy?