09:38 <d1b2> <Olivier Galibert> If a=Signal(8) and b=Signal(1), to get the equivalent with and of Mux(b, a, 0) is a & b enough or do I need a & Repl(b, 8)?

12:02 <whitequark> you need the latter, though at this point why not go with Mux?

14:01 <d1b2> <Olivier Galibert> My current (incorrect) code is something like

14:01 <d1b2> <Olivier Galibert> m.d.a1 += self.dt_1a.eq((self.dt_2 & ~(self.dt_sft | self.dt_a1 | self.dt_c2)) | (Cat(self.i_dt_sft, self.dt1[:7]) & self.dt_sft) | (0xa1 & sft.dt_a1) | (0xc2 & self.dt_c2))

14:01 <d1b2> <Olivier Galibert> where dt_sft, dt_a1 and dt_c2 are Signal(1) and the rest Signal(8)

14:02 <d1b2> <Olivier Galibert> probably mux is a better choice

14:02 <d1b2> <Olivier Galibert> (wd1772 data register, in case you wonder 🙂 )

23:57 <d1b2> <VA3TEC-Mikek-14362> Hi Josuah! Thank you very much! much appreciated! Yes that's Deca board that you have identified that I am using. So that helps me understand better, Ah, there is no ready made resource for the GPIO. This is where it was trapping me. :-s 😖 Your project is helping me very much understand how to do this properly! Thanks!! For your info, I also found this project, https://github.com/lawrie/ulx4m_amaranth_examples I was

23:57 <d1b2> following the GPIO setup that this person has there, But was getting errors in the python build. I hope that pointing you to this project with help you in yours! I feel VERY embarrassed about posting error messages that are probably very trivial for this group.. I have another question for the group here, can I help with some of this documentation? Once I figured some of it out myself! 🙂 Thanks again! MikeK