<mkal>
d1b2 that I saw but that's a very basic one. How does one include a larger module with many ports? Is there an API which generates the instance definition from a verilog module definition? after inferring busses etc? Suppose I have a module with a couple of axi streams, clock, reset etc. I don't want to type everything from the module.
<d1b2>
<zyp> there's no premade verilog parser, but it's python so you can script whatever you want
<d1b2>
<zyp> to hook up groups of signals all at once you could e.g. make adapter functions like this: https://paste.jvnv.net/view/OQXP9
<mkal>
I also see this discussion from 3 years ago and I'm curious if the stream abstraction has made it into amaranth library. If yes, a pointer would be appreciated.
<mkal>
the adapter idea is cool. I think I'll try to figure out how to use verible or https://github.com/MikePopoloski/slang to generate something like InstanceFromVerilog
<d1b2>
<Olivier Galibert> Not yet, there's work going on on the Interface aspects, which afaict are a requirement for a decent implementation of streams
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<d1b2>
<Olivier Galibert> Ok, I need help. I did something, not sure what, and now amaranth/sim is doing things that are impossible in my understanding of clock domains