00:47 <whitequark> <adamgreig[m]> "You can just call functions..." <- this isn't actually properly supported at the moment

00:49 <adamgreig[m]> What goes wrong? I'd have guessed the interaction with context managers might be weird but I feel like it's been ok

01:48 <whitequark> it's easy to accidentally write code that silently does the wrong thing if you call a function in the wrong place

01:48 <whitequark> like in an elif condition

14:31 <mithro> Has anyone here looked at https://github.com/alexforencich/cocotbext-pcie ?

17:22 <josuah> I did try cocotb a few times, but did not know about this PCIe cosimulator

17:24 <josuah> bl0x_: this is how LiteX does it sometimes it seems: https://gist.github.com/enjoy-digital/74f2d8cf0f7a1966428e930602f6705d#file-test_spibone-py-L24-L26

17:24 <josuah> any thought about this approach? is it avoided on purpose to keep signals and parameters separate?

17:24 <josuah> maybe 'Interface's would make that easier.

17:30 <josuah> > Although Amaranth does not support native code simulation or co-simulation at the moment, such support will be added in near future. -- https://amaranth-lang.org/docs/amaranth/latest/intro.html#the-amaranth-simulator

17:31 <josuah> mithro: there might need some additions to Amaranth for supporting something like this.

17:33 <josuah> <tpw_rules> isn't that what submodules are for

17:33 <josuah> I think (System)Verilog has tasks to fill the gap between submodules and copy-pasting codes around

17:34 <josuah> what about "transacitons": for instance, a alot of modules will have a Wishbone Interface/Record, then on top of that can be written something like "def read()" or "def write()"?

17:36 <josuah> something that would set all signals in the current context so that a Wishbone read/write can be issued at that cycle, eventually leaving-up some signal that tells "yes ok it was queued"

17:57 <josuah> hmm... maybe it would not work too well in practice, fail to make sense.

18:59 <mithro> whitequark: feel like this might be of interest to you - https://www.tomshardware.com/news/nvidia-downsizes-rtx-3050-to-size-of-hand

19:02 <josuah> related to the protocol it uses: https://www.usb.org/sites/default/files/D1T1-3%20-%20USB4%20System%20Overview.pdf

19:02 <josuah> good diagram on page 4

23:10 <josuah> hah, sorry that "Gist" from LiteX is for MicroPython!