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<
Stat_headcrabed >
Seems JH7110's display controller has cache coherence problem?
16:48
<
Stat_headcrabed >
Terrible
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<
Tenkawa >
Stat_headcrabed: I haven't seen any good reports on the IT GPU/Display implementations on Risc-V SBC's yet
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<
conchuod >
Stat_headcrabed: Got more on that?
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<
Stat_headcrabed >
conchuod: There's a fix for cursor flickering in downstream DC8200 driver, and the fix is that cache flushing
17:14
<
Stat_headcrabed >
So high possibility that this is a coherence problem
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<
Stat_headcrabed >
Display controller has AXI host port directly connected to NOC rather than front port
17:18
<
Stat_headcrabed >
Same for ISP, VENC, VDEC and GPU
17:19
<
Stat_headcrabed >
Btw, how to mark a peripheral as non-coherence in mainline?
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<
conchuod >
Put "dma-noncoherent" in the device or bus node
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<
Stat_headcrabed >
conchuod: thanks
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<
Stat_headcrabed >
So I think we need Esmil's JH7100 cache series land for this?
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<
Esmil >
..if anyone wants their Pioneer to boot faster ;)
18:31
<
bjdooks >
can the display memory be mapped write-through instead of write-back? might flush out updates faster to dram
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<
jrtc27 >
I don't think the JH7110 does Svpbmt
18:45
<
jrtc27 >
unless it crept into newer versions of SiFive's U74
18:46
<
jrtc27 >
if StarFive still managed to screw up cache coherence on their second go at the same SoC that's pretty sad and poor
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<
sorear >
i kind of hate that you need Svpbmt for PCIe
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<
sorear >
if you are accessing this channel through Matrix and want to continue doing so after EMS’ bridge goes away at the end of the month, please make yourself known
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<
jrtc27 >
you don't need Svpbmt if you don't care about performance :)
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<
ball >
What's a Svpbmt?
22:39
<
Tenkawa >
its a cpu extension
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<
ball >
Ah. Are there any sensible (or interesting) alternatives to PCIe?
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