sorear[m] changed the topic of #riscv to: Matrix users: #riscv:libera.chat will be ending operation NET Jul 25; please test #riscv:catircservices.org as a replacement | RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<whitequark[cis]>
BeagleV seems cool
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<Tenkawa>
whitequark[cis]: not enough drive io options for me
<unlord>
the last time I booted riscv with qemu, emulated disk IO was pretty slow
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<muurkha>
unlord: there are different ways to handle disk I/O in qemu, some of which are orders of magnitude slower
<muurkha>
drewfustini: awesome, congratulations on Ahead
<muurkha>
I wish I was getting Ahead
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<drewfustini>
Thanks :) The BeagleBoard.org executive director is looking into if we can get some allocated for the RISC-V Developer Board program https://riscv.org/risc-v-developer-boards/
<Tenkawa>
unlord: I'm getting around 300 mb/sec with my JH7110 NVMe setups
<Tenkawa>
decent enough for me
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<pabs3>
anyone know if any of the boards in the dev board program support USB gadget mode?
<drewfustini>
I think most can do client and host with USB
<drewfustini>
I believe the TH1520 controller supports this at least
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<conchuod>
ardb: I've not tested any of this stuff yet, so I do not have a ready-made qemu incantation for you.
<ardb>
great i was just scratching my head
<ardb>
about how to enable zvkned
<conchuod>
mmind00: (Heiko) might have some specifics
<conchuod>
It'll probably be something like "-cpu rv64,v=true,zvkned=true"
<ardb>
yep that seems to work
<conchuod>
There's some patches on the qemu list for a "max" cpu type that'll turn on everything possible, which should be handy for those of us who are not active qemu developers :)
<dzaima[m]>
on that -cpu you can also add on ,vlen=256 etc to choose a vlen (up to 1024 at least on the build I have)
<conchuod>
ardb: Did it work? I just tried to build that qemu and it dislikes zvkned=true
<conchuod>
Ahh, "x-z". I wonder why it needs that, the other extensions that I enable in my incantations do not do so.
<ardb>
not a clue
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<courmisch>
true "max" sounds impossible, like you can't have F and Zfinx simultaneously, no?
<palmer>
courmisch: ya, we had some chat there on the QEMU patches. So it's not clean cut like Arm and Intel, but there's at least some nominal notion of which is bigger (ie, F is bigger than F in X)
<palmer>
IIRC there's a handful of others floating around, stuff like the Zc bits
<courmisch>
and all the custom stuff has to be ruled out, but maybe QEMU has none so far
<palmer>
it's got some custom stuff
<courmisch>
I've only hacked the arm bits :$
<courmisch>
well, how that's going to work then? will XTHead stuff be in?
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<palmer>
I don't think anyone proposed adding XThead stuff to the max CPU
<courmisch>
IMO custom stuff should not be in max, but in all due fairness, XTHeadBA has stuff that Zba doesn't
<conchuod>
> We have mailing list based patch review so it would be great if you can send these patchs to OpenSBI mailing list.
<conchuod>
> The GH issues/PRs are a bit of a joke on that repo though, noone seems to engage
<conchuod>
I take this back, it's only the issues, not the PRs, that are like this.
<vagrantc>
ok, i guess i can follow up to the list too ...
<vagrantc>
isn't there a way to disable issues/pull requests? so as not to trick people into thinking they are actually used?
<conchuod>
You can disable pull requests, not sure about issues
<conchuod>
I think you can auto-close issues though
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<conchuod>
I think you can also use a .github directory to auto populate the PR/Issues text boxes with a template, which could also direct people, if closing is too harsh
<conchuod>
Also, seems I have it backwards. You can disable issues, but not PRs
<vagrantc>
github is kind of all about the PR, so kind of not surprising
* vagrantc
pesters the list too
<vagrantc>
ok, i wash my hands of this now :)
<conchuod>
:)
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<sorear>
i'm fairly certain aes64ks1/aes64ks2i can be used for aes-192 just as easily as for 128 or 256, although neither the spec nor the paper has code examples for the key schedule
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<ardb>
sorear: no not for the key schedule but for en/decryption itself it works fine
<ardb>
and generation of a key schedule should not be performance critical so there is no need to use those instructions to begin with
<ardb>
not sure why they even exist across all ISAs that have AES instructions
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<ardb>
every iteration of the key expansion algorithm XORs word n-1 of the previous iteration into word 0, where n is the number of words in the key
<ardb>
so AES-192 is fundamentally different, and the existing instructions cannot be used
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<sorear>
ardb: ignore me, I missed that the patch was about the vector crypto extensions and I also missed that vaeskf* are substantially more limited than aes64ks*
<sorear>
i think i've seen comments that some things switch keys fast enough for it to matter, although I haven't seen one myself; maybe if I was more familiar with IPsec and financial cryptographic protocols