sorear[m] changed the topic of #riscv to: Matrix users: #riscv:libera.chat will be ending operation NET Jul 25; please test #riscv:catircservices.org as a replacement | RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<Tenkawa>
Well I have both my VisionFive2 and Star64 JH7110's running nicely again... I notice there's a consistent load average ob boh using nvme of about .60 at full idle (one of 5.15 kernel one on 6.4 so it is an intriguing thing..
<Tenkawa>
er on both
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<geist>
SFENCE.VMA question that seems a bit ambigious in the privileged spec
<geist>
i'm fairly certain i'm reading too much into it
<geist>
but there's a comment about the situations when you should sfence.vma, for standard TLB flushing. most of them are obvious
<geist>
but one of them is "If software modifies a non-leaf PTE, it should execute SFENCE.VMA with rs1=x0. If any PTE along the traversal path had its G bit set, rs2 must be x0; otherwise, rs2 should be set to the ASID for which the translation is being modified."
<geist>
what's unclear is precisely in what situation it's describing. if its a) modifying a non leaf PTE while stuff downstream of it is still active, it makes sense because it's saying 'all the trnaslations below it may have changed'
<geist>
however, if it's b) you're detaching a page table because you've unmapped everything below it, do you need to do a full asid flush there? the answer is probably no, *but* it could be obliquely referring to an implementation having a page-table-translation-cache
<geist>
ie, like ARM and x86 does, where you may need to explicitly flush that
<geist>
i think it's the 'a' case, just not well described, because as far as I can tell no existing OS does a full asid flush on page table reclaim
<geist>
but then most of the existing OSes ported to riscv that i have source to are fairly dumb about TLB management on RV
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<sorear>
both a and b, I'm pretty sure
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<geist>
yeah the 'b' case is pretty gnarly, because that's a full asid dump every time you clean a page table. this is where i'd love for the manual to have a bit more clarity of the 'why' of this stuff
<geist>
and like i said i dont think for example any of the BSDs handle this case properly AFAICT, if in fact that's what you're supposed to do on PT unlink
<jrtc27>
FreeBSD doesn't use ASIDs
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<geist>
yeah but even without ASIDs, the way that section is written would imply you have to do a global TLB invalidate (ie, r2 == 0)
<geist>
ie, it's not really related to ASIDs per se, it's simply whether or not you do a ASID (or ASID 0) dump when modifying a non PTE entry
<geist>
er non-leaf
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<geist>
i'd say if the arch grew the need to maintain page-table-walker-caches, it should grow a new sfence.vma intruction variant for it, ie, how ARM has a bit in the TLBI instruction. that way it's a feautre you know you should need to use or not, based on it being in the feature list
<geist>
since i'm fairly certain existing implementations (ie, sifive and thead stuff) don
<geist>
dont have PT walker caches
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