sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<rneese> please think about joining as it would allow us to dev more as we can share thigns and pictures and post code snippets alot easier.
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<wbx> hi. http://sprunge.us/NHu9kG this is testandset as assembly, how could this be converted to gcc inline assembly? any takers?
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<terminalpusher> what's faster or smaller? `addi t0, t1, 0` or `add t0, t1, zero`?
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<muurkha> I think the first one can be compressed as a C instruction and is recommended as the implementation of mv to facilitate high-performance implementations
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<Esmil> f
<Tenkawa> Esmil: I was successful at attempt #1 of the 6.2 compile and overlsying that kernel on my existing test rootfs. Serial login was successful and now I will keep up with the changes and start compiling/testing
<Tenkawa> er overlaying
<Esmil> Cool
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