sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<pierce> Well I'm pretty stoked, preliminary patches for dotnet on RISC-V have been submitted! https://github.com/dotnet/runtime/issues/36748#issuecomment-1436325023
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<conchuod> geertu: 20230220123232.413029-1-marius.cristea@microchip.com
<geertu> conchuod: Nice! b4 am'ing
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<conchuod> The dt-binding (and thus the files in userspace) are different there compared to what we've been using in $VENDOR_TREE cos we had a pre-ACPI version of the driver.
<geertu> conchuod: Not very common to see a changelog for a v1 ;-)
<conchuod> Aw, I didn't realise that wasn't a lore link.
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<geertu> conchuod: np, I've configured my chrome to search lore based on message-id ("lore" TAB <paste-message-id>)
<conchuod> The ADC folk are pretty new to upstream, so hopefully Andy and Krzk aren't too harsh!
<conchuod> I tried to help them, but IIO stuff is beyond me!
<conchuod> Okay, that will be super helpful
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<conchuod> Thanks :)
<pierce> <pierce> "Well I'm pretty stoked, prelimin..." <- Oh it looks like some changes have already gone in! https://github.com/dotnet/runtime/pull/73385
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<gurki_> is there an intended way to hand over memory adresses to custom instructions within spike?
<gurki_> i basically want an instruction handing over three memory pointers, and modify that memory content within that custom instruction
<gurki_> i am sorry if my google-fu missed an example
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<gurki_> (i am aware that this does not directly translate to how stuff works in hardware, but for now i need a "hacky" workaround)
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<gurki_> oh. the vector instructions might provide a hint or two.
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