<LordDoskias>
namely the mret, result in an illegal instruction ?
<LordDoskias>
i.e when executing mret instead of jumping at the location written to mepc, it goes into the trap handler and mcause is 0x2
<LordDoskias>
i'm testing on qemu-system-riscv64
<jrtc27>
qemu has a special spec-violating case to help stop you shooting yourself in the foot
<jrtc27>
by default the pmp blocks all s-mode acceses
<jrtc27>
instead of letting you mret then trap immediately it will give an illegal instruction exception if mret'ing to non-m-mode and the pmp is unconfigured
<jrtc27>
otherwise if you have set up medeleg to delegate s-mode's own faults to itself you will end up in an infinite trap loop
<LordDoskias>
is this documented somewhere or there needs to be someone intimately familiar with qemu's internals on #riscv
<LordDoskias>
;D
<LordDoskias>
why would mret result in an immediate trap ?
<LordDoskias>
shouldn't it just jump to wherever mepc points with privilege as set in MPP ?
<jrtc27>
the mret wouldn't trap, the first instruction fetch after it would
<LordDoskias>
why ?
<jrtc27>
because the pmp blocks it by default
<LordDoskias>
and that happens only on qemu ? an actual physical implementation wouldn't act like that?
<jrtc27>
an actual implementation would trap on the instruction fetch
<jrtc27>
and end up in an infinite trap loop that's a pain to debug
<jrtc27>
(because stvec's target isn't going to be fetchable either)
<jrtc27>
qemu adds a special case to mret that stops you being able to reach that case, but isn't conforming
<LordDoskias>
so the correct workaround is to basically disable pmp ?
<jrtc27>
by making the mret itself fault
<jrtc27>
there is no workaround
<jrtc27>
your code is broken, qemu just changes its symptoms
<jrtc27>
the *fix* is to configure the pmp however you want it configured
<conchuod>
mmind00: smaeul how much of the d1 stuff is in -next?
<mmind00>
conchuod: not that much I think ... the plic already has a compatible, but there is a series from smaeul pending doing more cleanups ... and what I remember from talking with Samuel, I guess the "biggest" fish is the pinctrl driver (there is a slight difference in register offsets compared to "standard" allwinner socs, which requires adapting the pinctrl driver)
* mmind00
is off to bed now :-)
<conchuod>
plus maz has complaints about the irq patches