<conordooley>
atishp[m][m] Yeah, the boot cpu's call to update_siblings_masks() fails a malloc()
<atishp[m][m]>
your patches already fix the issue. Correct ?
<atishp[m][m]>
and I tagged wrong person starting with "con" ;)
<conordooley>
nono, I just logged in from work so names "real" here
<atishp[m][m]>
Ahh okay.
<conordooley>
My patches fix a different issue, that warning was cropping up on arm too and was silenced.
<conordooley>
I plan on sending a patch to soften the wording
<atishp[m][m]>
Ahh okay. I will take a look.
<atishp[m][m]>
* a look when you send the patch., * . Thanks.
<conordooley>
:)
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<conordooley>
wait youre getting a -2 not a -12 atish, so your problem is different
<conordooley>
you're failing the if (init_cache_level(cpu) || !cache_leaves(cpu)) check in detect_cache_attributes()
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<xypron>
Hello conchuod with CONFIG_SIFIVE_L2 the Polarfire Icicle board does not boot but loops with messages 'L2CACHE: DataFail @'. Does the L2 cache differ to what is on the Unmatched, Unleashed?
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<xypron>
conchuod: the FU540-C000 and the Polarfire SoC define the cache related PLIC interrupts differently. I will send a patch for the device-tree.
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<conordooley>
xypron sorry I didn't see your message earlier, not always paying attention here during the day ;)
<xypron>
conordooley: Did I use the wrong alias. Sorry.
<conordooley>
No
<conordooley>
I just have a different name in the webchat thing here than at home
<xypron>
:)
<conordooley>
firewall blocks irc stuff so gotta use this
<conordooley>
I assume the patch is a "Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")" ?
<conordooley>
At least the next time I do a devicetree I'll know what I am doing :)
<conordooley>
Between myself and whoever did the original dt (I forget who) we made a bit of a hames of it
<conordooley>
I've never had that l2 driver enabled, will add it to my dev configs now JIC it crops up again. Thanks
<xypron>
conordooley: On Linux 5.19 I see errors reported for PCI bar assignment and NVMe is detected but not usable in PCI slot. Is there already ongoing work for this?
<conordooley>
Yes
<conordooley>
soonTM pretty much, hopefully something will be sent soon.
<conordooley>
Part of that is fpga-fabric design related as the PCI is routed through there, but I won't try to explain since I am not too sure on the specifics..
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