sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<geist> i vaguely remember something about clang/lld not yet supporting most if not all of the linker relaxations for riscv
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<dramforever__> mort: IIUC, linker relaxation is only just being added to LLVM: https://maskray.me/blog/2022-07-10-riscv-linker-relaxation-in-lld
<dramforever__> So for now, yes, 'only GNU supports it'
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<organizedglobals> Off-Top: any RISCV or RISC+CISC ISAs that have AV1 encoders and decoders for workstation, gaming, streaming combo? really wanting the memory, OS, and file safety hardware accel found in ARMv9 as well, with additional hole filling. if everything is accelerated and accounted for in hardware we wouldn't need Rust or many mitigations.
<organizedglobals> we have to wait for flagship chips to make accelerators for common desktop environment/compositor features most likely
<organizedglobals> * Off-Top: any RISCV or RISC+CISC ISAs that have AV1 encoders and decoders for workstation, gaming, streaming combo? really wanting the memory, OS, and file safety hardware accel found in ARMv9 as well, with additional hole filling. if everything is accelerated and accounted for in hardware we wouldn't need Rust or many mitigations.
<organizedglobals> we have to wait for flagship chips to make accelerators for common desktop environment/compositor features most likely
<organizedglobals> tag me in response so i can come back and search
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