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<Hammdist>
I have a problem in that wfe seems to wake up all the time in QEMU (i.e., 100% cpu usage) even when I don't send sev. there is only one place in my code where I sev, and I put a write to UART there so I can see all the sevs that are being issued.
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<Hammdist>
I also put uart prints around the wfe and it's clearly spinning
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<Ermine>
heat: hi, why do you use actions/checkout@v2 for onyx actions?
<bslsk05>
github.com: COFFLoader2/COFF_Loader.c at master · Yaxser/COFFLoader2 · GitHub
<vai>
looking at this
<vai>
looks more matured up, I could not find any ELF32 source code
<vai>
most ELF32 implementations are bad
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<sham1>
4096 octets is the best page size, and that's a fact
<acidx>
heat: I like A5
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<sortie>
https://sortie.sortix.org/for/osdev/PXL_20231114_160434101.jpg ← Well I failed to install Windows 11 inside a Qemu VM on my Sortix laptop, but I did get all the way into the registry to set the secret variables to bypass the system requirements, but alas the installer still didn't think my VM was good enough :)
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<heat>
acidx, im not sure if my MMU takes A5 but i'll check
<sortie>
Windows 11's installer took a while to boot (like 5-10 minutes) but it was actually surprisingly usable and fast once it booted
<heat>
that hints that maybe IO just sucked
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<sortie>
A bit of a mix of factors but yeah, IO was part of it, unfortunately I couldn't fit a 6 GB file into my ramfs
<sortie>
So had to load the installer off disk
<sortie>
I think the older qemu is probably a bit buggy and doesn't have all the features, plus I could emulate features better, but whatever :)
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<sortie>
Probably the old TCG mode not having all the cpuid stuff that Windows 11 needs these days
<sortie>
But was fun to do shift + f10 and pop a command prompt and hack into regedit
<heat>
nah i think it should be fine on the CPU end
<sortie>
This is qemu 2.7.0
<zid>
sortie: I failed to install sortix in windows 10
<geist>
i'm kinda digging the 16K pages that lots of ARM folks are going to
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<geist>
it's alas a bit more unweildy in hex space, since it's not a nice clean 0x1000 but instead is 0x4000
<geist>
but. still easy to do the math in your head, since a page address is either 0, 4, 8, or c
<acidx>
sortie: isn't it a TPM requirement not being met?
<sortie>
acidx, yeah but that one can be bypassed which I did but it wasn't enough
<geist>
10 doesn't need TPM though right?
<geist>
it's 11 that does
<heat>
yeah
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<geist>
oh i see, 11 was installed
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<heat>
btw linux is going to start making use of contiguous ptes on arm
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<geist>
oh neat
<geist>
riscv has something similar too, so maybe that'll start getting used
<geist>
once the general mechanism for the upper level VM is in place to deal with pages like that efficiently
<heat>
yeah
<heat>
its a generic solution ofc
<heat>
(praise be the linux vm)
<Ermine>
x86 is sol?
<heat>
is what
<sortie>
stellar
<heat>
i dont get it
<heat>
x86 is stellar?
<Ermine>
sol = sorry out of luck
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<sortie>
oh not sol the star
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<heat>
AMD zen has a similar feature but without the bit IIRC
<sortie>
short on luck
<heat>
it just auto-detects contiguous PTEs with certain alignments IIRC
<heat>
because zen is a closeted arm microarchitecture
<moon-child>
I think aligned 32kb
<moon-child>
because that's 8 ptes which is one cache line
<heat>
yeah its written down somewhere but i can't be arsed to look
<moon-child>
amd is clearly plagiarising my principle of 'might as well use the whole cache line'
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<zid>
those bastards
<zid>
AMDAMD AMD, xeon is coal
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