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<gog>
dndos
<cloudowind>
mmorpgos
<zid>
dun dos?
<jimbzy>
I swear, my ideas are so ate up sometimes it makes other people put down their blunt... XD
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<gog>
lmao
<gog>
jimbzy lay down you're zooted
<jimbzy>
ADHD for the win.
<jimbzy>
Some people listen to music when they drive. I think about the stupid stuff I share with you all. ;)
<zid>
can I buy you an mp3 player
<gog>
:3
<jimbzy>
Only if it's a Zune.
<gog>
i knew a guy who was a big zune and general microsoft fan boy. shocking plot twist: he was kindof a dweeb
<gog>
and not the fun kind like me
<gog>
i know you're not a microsoft fan boy tho :P
<jimbzy>
I never actually tried a Zune, but I did have a Windows phone for a while and it wasn't terrible.
<gog>
it might have been fine if they didn't get there so late
<gog>
my roommate had a t-mobile early smartphone thingy
<gog>
and it was so close
<gog>
but it was before multitouch displays were really figured out
<gog>
so it was kinda clunky and still used the desktop metaphor
<jimbzy>
I need to get a new phone, but I don't want to carry a tablet in my pocket.
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<gog>
yeahhh mine is shattered
<gog>
and i've fixed it up to mostly usable with packing tape but it's wearing out and impossible to replace without destroying the screen
<gog>
so i need to do something about that at some point but i don't want to pay money for a thing i hate
<gog>
small screen bad screen
<jimbzy>
Yeah, I feel the same way.
<gog>
but i need it. i don't think the fare scanners on the bus will be able to read it anymore
<zid>
hello youtubes
<zid>
*funky keyboard solo*
<gog>
sick
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<immibis>
no paper tickets?
<immibis>
mcrod: if you don't watch much air disaster content, you might be surprised what it takes to make an aeroplane crash. They can fly with no engines just fine... for a while.
<zid>
It's like that joke that an escalator cannot break, only transform into stairs
<zid>
an aircraft doesn't fail, it just temporarily turns into a glider
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<immibis>
sometimes they do fail
<immibis>
like because someone repaired the bulkhead with a row of rivets into nothing
<sham1>
But that'd be exceedingly rare to happen, so yeah
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<immibis>
or the time the horizontal stabilizer fell apart in mid-air because someone didn't lubricate a jackscrew
<immibis>
nobody survived that one
<immibis>
there's a reason those kinds of things only happen once, though
<Mutabah>
yeah, although you could say that the crew weren't following procedure for that one
<Mutabah>
but after every accident training and procedures are updated to fix/reduce the holes revealed (usually successfully)
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<mjg>
ye majority of "what it takes to take the plane down" is failure to uphold proceduers
<mjg>
there is also a degree of redundancy between them to catch if someone fucked up
<Mutabah>
Swiss cheese model
<Mutabah>
A good crew can keep a broken plane flying into a "good landing"
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<mjg>
even so, some procedures used to be rather stupid
<mjg>
example: if there is fuel imbalance between tanks, just pump it to equalize, don't worry about anything bro
<mjg>
giggles are had when the imbalance stems from a leak
<mjg>
and then there was a design decision for safety which killed people
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<mjg>
there was plane which had a safety mechanism: if an engine vibrates past certain tolerance threshold, possibly damaging the wing, it falls off the plane
<mjg>
welp, one fell off on a residential building
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<mjg>
:]
<immibis>
there was the procedure to note and calculate fuel every 15 minutes while flying over the pacific, and the pilot dutifully calculated he had a fuel leak every 15 minutes and wouldn't make it to the other side, until he unexpectedly ran out of fuel and didn't make it to the other side
<immibis>
that plane was fortunately saved by some military base just barely within gliding range
<bslsk05>
'This plane RAN OUT of FUEL in the middle of the OCEAN!!' by Green Dot Aviation (00:24:44)
<sham1>
But the pilot was calculating the fuel every 15 minutes! Wot
<immibis>
ignore the clickbait title...
<immibis>
sham1: yes, just as the procedure said
<immibis>
the procedure did not include any step that if the calculation says you will run out of fuel in the middle of the ocean then consider diverting
<immibis>
it just said calculate and write down numbers...
<sham1>
I can only hope that the procedure has changed
<sham1>
Common sense, man
<immibis>
probably not. maybe they screen for common sense when selecting pilots.
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<immibis>
both pilots didn't think of it
<mjg>
totally avoid "air crash investigation" or whatever documentaries though
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<mjg>
informative content in 40+ minute video is 5 mins in total, if you are lucky
<mjg>
the rest is repeating it and for the most part interviews with families of people who died
<sham1>
Oh, kinda like true crime
<mjg>
well the biggest problem with tv documentaries is that they are intended for people with epsilon interest
<Mutabah>
and are designed with multiple ad breaks
<mjg>
and which were not expected to watch from the beginning
<mjg>
right
<Mutabah>
Mentour's videos are great though
<mjg>
so you come back from the ad break and get a repeat of majority of what was already said
<mjg>
which was not much to begin with
<mjg>
btw, re documentaries, there was a funny case concerning one about dinosaurs
<mjg>
apparently they did interview actual experts but edited it to misrepresent their statements
<mjg>
someone liked an idea which is widely considered bs and wanted to legitimize it
<bslsk05>
svpow.com: Lies, damned lies, and Clash of the Dinosaurs | Sauropod Vertebra Picture of the Week
<mjg>
sham1: years back i watched 2 different documentaries from 2 different series about some murderer
<mjg>
sham1: in one interviewed expert crimes were sexually motivated
<mjg>
sham1: in another one another expert said often times crimes are sexually motivated, but not in this case!
<sham1>
Okay good, at least it's a different expert
<zid>
sham1 do you want to pear program
<floyd>
bears loves pears apperently
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<zid>
bears love food generally
<zid>
There's a lovely competition that happens in some US national park, where they take a vote of all the bears and hold a voting bracket tournament thing for which one will end up fattest
<zid>
before they hibernate
<immibis>
can we call this submarine thing OceanGateGate?
<zid>
Their mistake was installing a gate on their submarine instead of a hatch
<immibis>
not only did they name it after the titanic and call it unsinkable, they also named it -gate for us
<immibis>
how many times can you tempt fate
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<vai>
hi
<vai>
its up to aims, what are your goals, are they realistic, for osdeving... so I was thinking I can make a CP/M clone for x86
<vai>
from my current multitasking project
<vai>
sort MP/M
<sham1>
immibis: and any controversy about this will be Oceangate-gate-gate
<mjg>
ocean? you mean water? :X
<sham1>
The submarine wasn't Watergate now was it
<cloudowind>
steve vai!
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<immibis>
vai sounds reasonable if that's what you want to do
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<immibis>
sham1 why would there be controversy about controversy
<immibis>
maybe people will argue about whether the transcript is real
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<ddevault>
I am somewhat puzzled by this ATA IDENTIFY response
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<ddevault>
via qemu, the model name (QEMU HARDDISK) is there (with stupid endianness nonsense, but we can't all be perfect), but the first word is 0x4000? I would have expected 0x8000 from a reading of the ATA spec
<ddevault>
err, no, I misunderstood. bit 15 should be zero. we good
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<gog>
hi
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<sham1>
hi
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* vdamewood
gog.give(fishy)
<gog>
GOG_LOG_INFO: fishyEventCallback() returned DO_CHOMP
<vdamewood>
Reading that, I just got a disgusting idea: A kernel written in C++ with Qt.
<sham1>
Could be worse
<sham1>
A kernel written in C++ with WinAPI API design
<vdamewood>
sham1: I'm not sure I can... handle that.
<sham1>
HANDLE aside, I do wonder how a OO kernel would look. Like the kernel would expose various objects and let you call them
<sham1>
vDSO might be useful for that
<vdamewood>
I think Haiku (and BeOS was) is designed like that.
<sham1>
An entire OS built around objects or an actor model in general. Now there's an idea
<vdamewood>
Sounds like NexT, except NeXT didn't do it so far into the kernel.
<GeDaMo>
Smalltalk? :P
<sham1>
Smalltalk… I mean yeah, that works. Smalltalk isn't async necessarily
<vdamewood>
Well, NeXT did use objective C, which was basically C with Smalltalk stapled on.
<sham1>
Maybe a language influenced by Strongtalk
<sham1>
Because I like type systems
<GeDaMo>
Wasn't Strongtalk influenced by work on Self?
<sham1>
I think so
<sham1>
Yeah, it was
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<sham1>
Anyway, there are other ways also to do this, like making COM first-class in the OS
<sham1>
> In the 2010s, some of Apple's personnel and design concepts from Pink and Purple (the first iPhone's codename)[8][9] would resurface and blend into Google's Fuchsia operating system. Based on an object-oriented kernel and application frameworks, its open-source code repository was launched in 2016 with the phrase "Pink + Purple == Fuchsia".[10]
<sham1>
Of course, a COM-like OO protocol stuff really would make sense for a microkernel
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<mjg>
i don't know how it differes from stock splay trees
<heat_>
no, that wasn't maple syroup
<heat_>
the maple syroup people are doing significant vm cleanups
<heat_>
most of the really shitty code is gone now
<mjg>
noice
<mjg>
anyhow
<mjg>
so linukkkz rolls with upfront strlen and then memcpy
<mjg>
while freebsd has the original obsd implementation rolling with per-byte ops
<mjg>
which for this lol case is probably faster since normally strings are short af
<mjg>
this could be patched to eprform though
<mjg>
this entire debacle makes me support RUST
<mjg>
hm... so how do they do zero overhead strings
<heat_>
zero cost strings
<mjg>
they literally don't even use memory!
<mjg>
let s = String::from("Hello");
<mjg>
takes_str(&s);
<mjg>
> This will create a &str from the String and pass it in. This conversion is very inexpensive, and so generally, functions will accept &strs as arguments unless they need a String for some specific reason.
<mjg>
oho
<mjg>
epsilon cost string handling
<mjg>
> A String is made up of three components: a pointer to some bytes, a length, and a capacity.
<mjg>
liek 0 fucking cost mate
<mjg>
compared to a bare string
<mjg>
i'm guessing two uint64
<nortti>
&str would be the bare string, from what I understand, while String is a modifiable container
<heat_>
yeah assuming &str is a normal string view converting a String into a &str is super cheap
<mjg>
so they implement strings on top of "vectors"
<heat_>
right, as one normally does
<nortti>
the String "class" is an optimization of Vec<u8> from what I understand yeah
<heat_>
std::string works similarly
<mjg>
i'm trying to find actual memory usage
<heat_>
i dont know how String works but std::string has SSO
<nortti>
I believe rust stdlib containers don't do that, so you'll need to use third-party crates for that
<sham1>
There's also Str tbf, which more resembles your pointer+size idea
<nortti>
isn't the Vec stored inline?
<mjg>
can it be if you pass it around?
<sham1>
No, Vecs are heap allocated
<sham1>
Well, the capacity is heap-allocated
<nortti>
right, I mean the Vec structure
<nortti>
mjg: why couldn't it be?
<nortti>
even C allows you to pass structures by value
<mjg>
for an ez case where you create it for a temporary case
<mjg>
before a call to something, you do the call, then you drop the string
<nortti>
how do you mean?
<mjg>
i can see stack usage as viable
<mjg>
but if the string needs to persist, say you add it to a hash
<mjg>
you seem screwed?
<mjg>
unless you strip it to c-like
<nortti>
if you add it to a hash table, either the hash table owns it (and so stores the 24B String struct in its structures) or it borrows it (in which case it stores a &str which is 16 byte pointer + size)
<mjg>
sounds like still a waste
<mjg>
well, not necessarily waste, but definitely an overhead
<mjg>
if i was C-ing it i would have size (probably inted) followed by the string itself immediately
<mjg>
even if i had to roll with 64-bit size, i still use less
<nortti>
might be that RawVec contains the capacity
<nortti>
rust allocator API does not require the underlying heap manager to track allocation sizes out-of-band, rather requiring memory size to be passed in to the memory block freeing function too
<bslsk05>
doc.rust-lang.org: size_of in std::mem - Rust
<mjg>
now that i asked, the answer i linked has it ;)
<mjg>
well sizeof says 24
<mjg>
ok, for shite usage they indeed get allocated on the stack
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<mjg>
now i'm kidn of curious why they went with jemalloc though
<nortti>
https://github.com/rust-lang/rfcs/blob/master/text/1974-global-allocators.md#jemalloc quoth "Rust's default allocator has historically been jemalloc. While jemalloc does provide significant speedups over certain system allocators for some allocation heavy workflows, it has has been a source of problems. For example, it has deadlock issues on Windows, does not work with Valgrind, adds ~300KB to binaries, and
<bslsk05>
github.com: rfcs/text/1974-global-allocators.md at master · rust-lang/rfcs · GitHub
<nortti>
has caused crashes on macOS 10.12. See this comment for more details. As a result, it is already disabled on many targets, including all of Windows."
<nortti>
so I guess it was some performance optimization realatively early on
<mjg>
luller
<mjg>
fwiw i think it works with valgrind just fine, on freebsd at least
<bslsk05>
internals.rust-lang.org: Jemalloc was just removed from the standard library 🎉 - announcements - Rust Internals
<mjg>
i *suspect* what they mean is having it bundled does not
<nortti>
probably
<nortti>
s/been jemalloc by default/shipped jemalloc as part of the normal install/
<mjg>
- [The default allocator has changed from jemalloc to the default allocator on your system.][55238] The compiler itself on Linux & macOS will still use jemalloc, but programs compiled with it will use the system allocator.
<mjg>
huh
<mjg>
hue
<mjg>
Type size_of::<Type>()
<mjg>
char 4
<mjg>
fucking with c programmers, aren't we
<nortti>
do you know how swift does char?
<sham1>
Well it's actually a Unicode codepoint
<sham1>
That's nice
<mjg>
nortti: no
<sham1>
There's also c_char
<mjg>
i'm just joking
<mjg>
in c sizeof(char) is defined to be 1
<mjg>
so
<mjg>
funzy
<nortti>
mjg: it's an extended grapheme cluster, which aiui means chars in swift are dynamically sized
<sham1>
And meanwhile go has runes
<nortti>
I think the rune terminology comes from plan9, as they were doing unicode code point handling in C where char was kind of already taken
<sham1>
Makes sense. A 32-bit signed int works fine for Unicode codepoints + some other things you can put in-band like EOF
<sham1>
Also why getc for example returns int
<nortti>
aye
<mjg>
:]
<mjg>
people are notorious for char c = getc(); though
<nortti>
ooh that's gonna be fun with unsigned char platforms
<mjg>
they were notorious for gets as well
<mjg>
so
<sham1>
People are notorious for that, and that's why they fail
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<gog>
worst person you know is having a terrible year
<gog>
life is pretty good
<mjg>
would you pet elon
<mjg>
... with a stick
<sham1>
prr...?
<mjg>
earlier today i accidentaly found out that one of hyperloop spawns -- virgin hyperloop -- was a venture by a gazilionbillionaire
<mjg>
i though that's a lol startup which got fundign as a way of laundering money
<mjg>
looks lke the onwer genuinely thought something is there
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<heat_>
hi im ack
<heat_>
back
<heat_>
or im ack, whatever
<heat_>
i am now ack
<gog>
akc ack ack ack
<gog>
ah it's good to laugh
<heat_>
gog on dat tcp connection
<heat_>
no delayed acks here!
<Ermine>
gog: may I pet you
<gog>
Ermine: ack
* Ermine
pets gog
* gog
syn-ack
<heat_>
the fuck
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<heat_>
pls read rfc793
<heat_>
you cannot do ack and then syn-ack
<heat_>
you're prone to get a RST back
<gog>
oops
<gog>
i don't know tcp
<Ermine>
it's gcp
<Ermine>
gpp*
<heat_>
the gall of these people
<Ermine>
gog petting protocol
<heat_>
have you never implemented your own tcp/ip stack??
<gog>
i haven't
<heat_>
smh my head
<gog>
i know
<heat_>
full stack development my ass
<gog>
hhhh
<heat_>
if you can't do the whole OSI layer model, you're not a full stack developer but merely frontend
<gog>
sorry i'm working on writing the whole operating system stack
<heat_>
and you do not want to be a frontend developer do you?
<gog>
it's taking me a while
<gog>
i've got a frontend you can develop
<gog>
right here
<heat_>
helo u need operating sytsem stack?
<gog>
yes i need one ready made up for grabs
<heat_>
github.com/heatd/Onyx very good operating system stack i recomend veyr very god
<bslsk05>
heatd/Onyx - UNIX-like operating system written in C and C++ (7 forks/58 stargazers/MIT)
<gog>
ok but does it have extensive tutorials
<heat_>
you have a plenthora of rants of mine on #osdev irc logs
<heat_>
that should do for docs yeah?
<gog>
no i need you to teach me directly
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<sham1>
openjdk port when
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<mcrod>
hi
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<sham1>
hi
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<zid>
I ran out of 醤油
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* mjg
forks onyx
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<mcrod>
i'm miserable today
<mjg>
sleep until tomorrow
<mcrod>
i wish that were possible
<zid>
see, me running out of soy sauce has ruined everybody's day
<sham1>
It might also ruin my night and sleep. We'll see
<gog>
hi
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* gog
brings zid soy sauce
<zid>
can you bring food to put it on too
<zid>
I ate a random pack of noodles I found
* gog
brings zid fried egg noodles
<zid>
indeed, I fried them, and they were egg noodles
<gog>
i know what oyu like
<mcrod>
wtf
<mcrod>
i want food
* gog
brings mcrod a chicken leg and rice
* mcrod
chomp
<zid>
out of damn near everything rn
<zid>
that was the last shallot, and the last of the garlic
<zid>
and there was no soy
<gog>
time to go to iceland
<zid>
ikr
<mcrod>
iceland has chili and fish
<gog>
yes it does
<zid>
and frozen pizzas
<gog>
it has many other produts too
<zid>
I found one more piece of food at least for later
<gog>
idk about the UK but it's actually among the worse grocery stores here lol
<gog>
it's more like a bodega
<zid>
half a pack of rich tea biscuits, and we have butter
<zid>
that's a meal
<gog>
i'm all about that Bónus
<zid>
iceland is cheap and frozen
<zid>
it's more like a specialty store than a full supermarket
<nortti>
< gog> idk about the UK but it's actually among the worse grocery stores here lol ← reminds me, they tried to sell tesco storebrand products as a luxury brand in finland and estonia
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<gog>
nobody can beat Bónus on prices here, not even costco
<zid>
The suffering is what makes it taste good, so it's cheap AND good
<mcrod>
nortti are you named after -fno-rtti?
<zid>
I thought he was naughty
<zid>
but spelled like a fin
<nortti>
*they
<mcrod>
oh, finnish for nerd
<zid>
get default he'd
<nortti>
but no, I'm named after nörtti, the finnish word for 'nerd'
<gog>
do you use arch linux
<gog>
btw
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<zid>
gog you can't just go and ask someone if they're a deviant out loud like that
<gog>
yes i can i'm a deviant too
<nortti>
gog: at the moment I'm actually running windows 10
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<gog>
how normie
<zid>
I am running w10 :(
<zid>
I miss w7
<nortti>
but on my main computer I use debian
<gog>
why do you want to run an unsupported windows
<zid>
Only cool thing about w10 is wsl2, which just about barely works, rest is shit
<gog>
also windows 10 best windows
<gog>
what happened to windows 9
<zid>
windows v x is just windows v x-1 but with more shit to try to turn off
<nortti>
< gog> why do you want to run an unsupported windows ← because it's not yet unsupported (that's going to be in 2025), and becase a 2017 surface pro is too old to run win11
<zid>
rumor says it's to stop bugs in programs doing if strstr(winver, "Windows 9")
<gog>
oh
<gog>
i didn't realize windows 7 i sstill supported
<zid>
for windows 95 and windows 98
<gog>
that actually makes a lot of sense
<Bitweasil>
That's what I've heard as well - enough stuff was searching for the "Windows 9" string that it would have rendered a lot of stuff weirdly broken.
<nortti>
gog: oh, sorry, misunderstood that as being re. mine. I think windows 7 went out of support 2021 or so
<zid>
I somehwat succeeding in turning off some of the shit differences between w7 and w10
<zid>
but it isn't truely possible
<heat_>
sham1, i've briefly looked at openjdk and it didn't seem hard to port. but then i was like fuck that
<heat_>
so i fucked that
<zid>
so I have 200 more processes running than w7 had
<Bitweasil>
And it makes sense, if I wanted to detect "Windows 95/98 SE whatever," I'd probably do the same thing.
<zid>
and it contacts bing all by itself and shit
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<heat_>
thank fuck it contacts bing
<heat_>
bing is the superior search engine
<Bitweasil>
I won't run Win11 at this point. Win10 has gotten too chattery with Microsoft.
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<gog>
i'm guessing win32 didn't offer any more offocial way with enums and shit to test the current version of windows
<Bitweasil>
And I hate online accounts.
<zid>
I don't want to fucking search engine when I am looking for files
<gog>
you don't need online accounts for win11
<Bitweasil>
I also, even more, hate "having to fight with the OS installer to get an offline account."
<zid>
why the fuck would I type n1256 into my run bar and want it to *bing* for that
<Bitweasil>
I thought it required them?
<gog>
true
<gog>
no i use an offline account
<mcrod>
i was pretty done when I installed windows 11 and saw tiktok installed
<zid>
I couldn't figure out how to not make an msn account on the one time I reinstalled w8 for someone
<mcrod>
tiktok is also blackholed at router level, except for my girlfriend, sadly
<Bitweasil>
Doesn't change the fact that it's an advertising delivery and behavioral extraction platform with a side effect of running some apps you didn't pick from the recommended distraction list...
<zid>
but w10 didn't relaly ask me to
<Bitweasil>
gog, did you have to mod the install to get that? The process I'd seen was something about popping up a cmd prompt and modifying the installer before it ran, or doing some offline mods to install media.
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<Bitweasil>
Which is beyond absurd.
<Bitweasil>
I shouldn't have to fight my OS like that.
<gog>
i don't rmember what i did
<mcrod>
yeah you have to bring up a command prompt and type something/BYPASSRNO or something
<gog>
it was like a year ago
<zid>
w10 didn't ask me shit
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<gog>
i didn't do anything like that
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<zid>
w8 was the bastard about that
<Bitweasil>
It used to be fine. Then it was only fine if you weren't network connected.
<gog>
i just clicked something iirc and i was able to do an offlin eaccount
<Bitweasil>
Hm, ok.
<mcrod>
definitely can't do that anymore
<gog>
maybe it's not offline?
<gog>
i actually don't know lol
<Bitweasil>
I actually just hate computers anymore. :)
<gog>
i'll report back tomorrow morning
<mcrod>
source: i had to install windows on vmware at work recently
<zid>
yea I think it asked me to sign up/log in to my msn account or whatever, or I could press skip
<zid>
and I did
<mcrod>
instant "sign in with your microsoft account!"
<mcrod>
unavoidable
<zid>
and it hasn't mentioned it since
<mcrod>
also, the command is OOBE\BYPASSRNO
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<Bitweasil>
That Microsoft considers which email address is logged into the computer so valuable is part of why I want them to have none of that info.
<mcrod>
er, NRO
<Bitweasil>
*nods*
<gog>
yeahhhh
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<zid>
Bitweasil: imo it's why they wanted a hard TPM requirement in w11
<zid>
so they could tie hardware to users
<Bitweasil>
Can you stuff Win11 in a KVM VM? I've never actually tried.
<gog>
i just don't remember having to register an account but maybe i forgot on purpose
<Bitweasil>
I suppose you could probably add a pretend TPM and such.
<zid>
the same 'open regedit during the install process by hitting ctrl-f8 and disbaling the requirement' trick worked last time I chedkt hough
<gog>
or the version of the installer i had didn't require it
<Bitweasil>
zid, yeah, users is the right term. First install's free, man. All the cool kids use it... etc.
<gog>
actually no
<gog>
i remember
<gog>
i installed w10 and upgraded
<Bitweasil>
For a while, Win11 Pro was fine without online accounts.
<Bitweasil>
And then they changed that around.
<Bitweasil>
Ah, an upgrade would do it.
<zid>
'upgrade'
<zid>
I'd still be happy on xp64
<zid>
if they addd hpet support and nvme trim
<gog>
are there any xp mods that do that
<nortti>
does xp64 have any nvme support?
<gog>
i know there's one that tries to backport as much as possible
<nortti>
oh, okay. I thought it had its own hardare programming interface
<heat_>
it does
<heat_>
nvme is completely different from AHCI
<zid>
It does yea
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<zid>
but the OS layer (rather than the driver layer) only cares about new commands
<heat_>
like, radically different. even supports NVME over TCP
<zid>
like trims and stuff
<zid>
pointless the driver s upporting it if the OS is never going to issue it
<mjg>
heat_: i know the paper, it is a little funny
<mjg>
while it is true lololocks are dangerous, it gives way too much credit to mcs
<mjg>
and disses ticket locks on linux, even though their implementation was SUBOMPTIONAL
<mjg>
namely afair they would spin with one pause before each load from the lock
<mjg>
obvious optimization idea: you check how far off are you from the ticket adn spin that much instead
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<mjg>
also most published lock benchmarks are bogus
<mjg>
especially so if they involve backoff
<geist>
hmm, sort of subtle detail of the riscv paging and TLB shootdowns i didn't catch before
<mjg>
typically authors of the paper will roll with a dumbfuck value
<geist>
it's not so explicitly spelled out, but it seems the arch *also* has a page table cache in addition to the TLB cache
<Bitweasil>
What's that caching, then?
<geist>
it's not really mentioned *except* it says you should `sfence.vma address, zero` whenever you modify a non leaf PTE
<Bitweasil>
I'd expect the tables to be in L1 or L2, but not an explicit cache.
<geist>
which basically equates to 'dump the entire TLB'
<Bitweasil>
Oh, so maybe higher level entries cached somewhere?
<geist>
ie, it doesn't have a variant of sfence like ARM64 does that dumps non terminal (ie, non leaf) ptes explicitly
<geist>
you have to dump that entire ASID
<Bitweasil>
Hm.
<Bitweasil>
I need to spend some time curled up with the RISCV docs.
<geist>
yeah, page translation cache is a common optimization. all arches basically hve it, it's basically other TLB entries that cache a flattened version of the page table walk to let the cpu skip to the end
<geist>
think of the page table entry cache has holding something like
<heat_>
x86 doesn't I think?
<geist>
'for this range of VAs, with this ASID, the final leaf page table is at PA'
<heat_>
or at least it's severely neutered
<Bitweasil>
*nods* Makes sense.
<geist>
x86 does. the intel manual says 'you dont have to worry about it, invlpg deals with it for you'
<Bitweasil>
heat_, who knows what x86 has or doesn't these days... probably present on the P cores but not the E ones, or something. Or the other way.
<Bitweasil>
Ok.
<sham1>
Not being then would be quite weird.
<heat_>
i know AMD has a chicken bit for "i'm aware this is a thing", we've discussed that before
<geist>
AMD cpus explicitly have it, and there's a CR4. bit to enable explicit maintenance
<geist>
with the idea that you can hypothetically get better usage by opting in to only flush it when necessary, ie like ARM64
<Bitweasil>
Yeah, ARMv8 cache and TLB flush stuff is... flexible.
<geist>
the hint that this exists in RISCV is in the section of the priviledged spec talking about sfence.vma
<geist>
it says
<geist>
"The following common situations typically require executing an SFENCE.VMA instruction:"
<geist>
...
<geist>
"If software modifies a non-leaf PTE, it should execute SFENCE.VMA with rs1=x0. If any PTE along the traversal path had its G bit set, rs2 must be x0; otherwise, rs2 should be set to the ASID for which the translation is being modified."
<Bitweasil>
And if rs2 is x0, it blows the whole thing?
<geist>
badsically sfence with rs1=x0 is a 'full flush of this asid' and rs2 holds the ASID. if you put a zero reg in rs2 it becomes a 'flush all asids'
<geist>
right
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<Bitweasil>
Gross.
<geist>
sfence.va zero,zero is a full dump of the TLB, including global pages, on all asids
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<geist>
now i gotta figure out precisely what
<geist>
"If any PTE along the traversal path had its G bit set..." means
<geist>
i think that basically means 'all upper page table entries, which can have a G bit set *and* the final PTE entry'
<geist>
ie, you're flushing a global page
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<geist>
makes sense that you'd want to in that case do a `sfence.va address, zero` because you're basically doing a 'flush this VA across all asids' because it's global
<heat>
modern windows booting on an SSD is so fucking fast
<heat>
and this is SATA!
<geist>
what's grody in that interpretation is if you futz with an inner page table entry in that case, you hae to dump *all* the TLB on all asids
<Bitweasil>
heat, it's got nothing on U320 SCSI and XP on a 15k drive.
<Bitweasil>
XP was so much smaller and lighter.
<Bitweasil>
geist, that's pretty much how I read it.
<heat>
Bitweasil: nothing beats not having to boot again
<Bitweasil>
Well, hm. Maybe only if anything *to* that layer had the G bit set?
<heat>
this just hibernated
<geist>
so it begs the question: is there value to setting the G bit on inner kernel page tables if all of the final nodes in the tree are also G
<Bitweasil>
Those last nodes would be in the TLB directly.
<geist>
so if in the kernel you have a G bit on the final PTE, but the inner PTEs *dont* then does it not globally cache the page table translation?
<Bitweasil>
If you're using large page mappings (I assume those exist?), you really shouldn't have too many TLB entries for the kernel to worry about.
<geist>
yes, large mappings exists all the way up, which is hwy they're careful to call things leaf and non leaf PTEs
<Bitweasil>
You'd presumably have the leaf entry cached, but possibly not the upper level entries on the way through. However, if you're hitting the TLB entry, the upper stuff wouldn't matter... I think?
<geist>
yeah but i'm thinking about the page table trnaslation cache
<geist>
are those entries global or not? that seems to be what they're implying with the quoted text above
<geist>
ie, if the G bit was set in any of the non leaf PTEs on the way down, then the translation cache is also global
<geist>
and you need to dump it accordingly
<Bitweasil>
In the words of ARM, "IMPLEMENTATION DEFINED"?
<geist>
well, no it's explicitly telling you how to deal with it, it's just a little unclear as to precisey why
<geist>
because ther'es AFAIK no real theory of operation
<Bitweasil>
Sure, my guess is that the exact details will vary depending on who wrote the core.
<geist>
this section of the manual is very terse, bascially assumes you already know the theory of operation of TLBs
<Bitweasil>
"This is permitted to be an optimization, so you should code assuming this is needed."
<Bitweasil>
idk. I should read those manuals at some point, once we have ARMv8 done. :)
<geist>
indeed. it's definitely written assuming a high end implementation does implement all this stuff
<geist>
the riscv manuals just dont tend to mention that as much as 'this is how they work'
<Bitweasil>
Or learn to grow stuff and raise chickens.
<heat>
geist: had to check, on x86 G does nothing on non-LEAF PTEs
<heat>
it's ignored
<geist>
heat: yeah i was surprised to see that G *does* on riscv
<heat>
oh, it does?
<heat>
fuck
<geist>
heat: actually worse, on AMD it fires a #GP, i found this out the hard way.it's reserved on AMD vs intel. one of the subtle differences
* heat
takes a mental note to check that out in a few hours
<heat>
oh haha someone here struggled with that for a bit
<geist>
heat: yeah re-read that section careful in the riscv manual, i'm really going over it with a fine tooth comb
<geist>
but yeah riscv manual says the G bit is non reserved on non leaf PTES, and it applies to everything below. basically ors in a G bit
<geist>
which begs the question: is there value to doing that if you're always going to map everything in the kernel, say, as G
<geist>
what does that *change* aside from just double checking
<heat>
oh jeez i also need to fix G on non-leaf PTEs for my x86, i have some uses there
<geist>
normally i'd think nothing at all, but then in the sfence.vma stuff it starts to make you think, because of that ambiguous text about it
<heat>
hmm yeah that's odd
<geist>
the riscv manual would be nicer if it showed you PTEs for leaf and non leaf. but it only shows the leaf version and then in text says 'these bits are not used in non leaf'
<heat>
maybe it's just a "clean-up" of the x86 behavior?
<Bitweasil>
Oh, like the ARMv8 upper level attribute stuff, NSTable/NXTable/etc? Makes sense.
<Bitweasil>
My impression is that RISCV is "more ARM than x86" in a lot of ways.
<geist>
in paging it is more x86 than arm, in general
<Bitweasil>
*nods*
<geist>
if there was a 1-10 scale where 1 is arm and 10 is x86, i'd say it's like a 7
<Bitweasil>
I've been buried in the ARMv8 MMU for some while now.
<Bitweasil>
It's got a lot of weird little extensions, before you even start in on the hypervisor behaviors. :/
<geist>
ie. single page table, needing to do IPIs of some form to shoot down things, etc
<geist>
and ASIDs are optional
<geist>
it does make the commentary that doing IPIs instead of cross-cpu ipi flushing may be a high performance cpu thing
<geist>
s/cross-cpu ipi flushing/ tlb flushing
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<Bitweasil>
... that makes a lot more sense. :)
<Bitweasil>
I've lost a lot of my interest in playing with the weird little ARM SBCs since I got into Qubes.
<geist>
basically in the manual it says that in the long run with very high end systems with craptons of cpus, doing IPI shootdowns may be more performant than having hardware cross-cpu TLB shootdown like ARMv8 does
<Bitweasil>
I know the RISC-V SBCs are coming along nicely, but I also kind of enjoy things sort of mostly working...
<Bitweasil>
And I expect the software ecosystem on RISC-V is far worse than on ARM right now.
<geist>
it is. a few more years there should be some more high end impls
<Bitweasil>
*nods*
<Bitweasil>
Qubes on x86 is oddly functional.
<geist>
well 64bit stuff when i say high end. in the embededed space riscv is starting to take over
<Bitweasil>
And keeps stuff nicely siloed too.
<Bitweasil>
Yeah.
<geist>
but in that stuff the arch is far less important to most folks
<Bitweasil>
Agree, you're not doing cross platform stuff in the first place.
<Bitweasil>
As long as it builds for *your* uC, it's fine.
<geist>
side note did you see the vid about the guy making a riscv cpu in terraria?
<geist>
right, it's funny because they basically did the exact thing that x86 did
<geist>
ARMv8 paging is functionally ARMv7 LPAE
<Bitweasil>
Yeah, with a few extensions to it.
<geist>
which came long very late in the game, and was a direct analogy to the PAE x86 extensions that got extended to 4 levels in x86-64
<Bitweasil>
And now 5! :D
<geist>
yah
<Bitweasil>
For... I have no idea who (a) uses that much VA space and (b) could pay Intel to do this.
<geist>
at least riscv picked that up from day one. 5 levels is just a mode you switch to
<zid>
big VA space is fun, lets you use your TLB as a hardware trie impl.
<Bitweasil>
They support... what, 52-bit?
<geist>
and you can switch on the fly, so if you're careful how you map the kernel, and leave the kenrel space to 38 bits, you can arrange for it to be mapped equivalently in sv39, sv48, sv57 and switch between them on a process by process basis
<Bitweasil>
ooooh. Ok, that's slick.
<geist>
in 48 and 57 you'd just be limited to the top little part of the larger kernel VA space
<geist>
(at least i think so, haven't tried it, but it seems like that'd be doable)
<Bitweasil>
"Yeah, gotta double clutch this process switch, we're going from 3 level straight to 5 level!"
<geist>
pretty much, but smartly the SATP register holds 3 things: the mmu mode (including disabled), the ASID, and the pointer to the page table, so you can switch
<Bitweasil>
You'd have to use the 32-bit style "physical memory window page" thing if you had a lot of RAM, or swap kernel modes, but I can see it working decently enough.
<geist>
yah currently i'm only using sv39 since that's the only real thing that's supported with real hardware at the moment
<geist>
qemu emulates the full monty, but that's aspirational
<Bitweasil>
Do you have any of the pointer tagging/sealing/top byte ignore stuff that ARMv8 has?
<Bitweasil>
Obviously not the full upper byte with sv57, but in general.
<geist>
i think there's something like that in the works, but not an extension yet
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<heat>
i do sv48
<geist>
actually i may be written down now, i think the TBI was basically going to be 'however number of bits are currently unused'
<Bitweasil>
That's one complaint I do have about x86's 64-bit modes, you waste a lot of pointer bits and can't use them.
<geist>
so in SV57 i think that'd get you 7 bits
<Bitweasil>
*nods*
<Bitweasil>
There's the TBI, and then there's a bunch of other sealing/tagging stuff that uses "whatever's left, sort of," but I've not implemented it yet.
<Bitweasil>
I was seriously trying to build an x32 Linux image for a while for low memory machines.
<Bitweasil>
(64-bit mode, 32-bit pointers)
<geist>
yah there's a bit of question if in TBI style things you make bit 63 mean 'which half of the aspace' or you use the top most implemented VA bit
<geist>
i think the riscv spec is doing the latter
<Bitweasil>
That's how ARM is doing TBI.
<Bitweasil>
Bit 55 determines which you saturate to.
<geist>
yeah
<geist>
iirc the x86 one may be doing the other? probably to maintain some sort of notion of canonicalism
<geist>
one of them is doing bit 63, which seems like a PITA
<geist>
but i guess it lets you do a quick negative/positive check
<zid>
gentoo has an x32 mode, I briefly tried to figure out hwo to set it up and gave up after a few mins :P
<Bitweasil>
I think x86 is bit 63, but you can't use the other bits in there for anything else.
<geist>
i really dislike TBI stuff, but it's what software/security folks want so it's one of those pains in kernel programmers ass, but that's how it is
<Bitweasil>
zid, yeah, it supports it, but it doesn't actually *work* in 2023.
<Bitweasil>
Why?
<Bitweasil>
Saves memory.
<zid>
yea I don't feel like it did
<Bitweasil>
And you can mostly ignore it.
<zid>
I couldn't install it because of random 32bit vs 64bit differences in trying to set up the chroot
<zid>
I could possibly have gotten it to work, but I couldn't be bothered to figure out how
<Bitweasil>
"You have to store 64 bits, but can only use 48 of them!" is the sort of mustache twirling evil that you'd expect out of a Bond villain.
<Bitweasil>
zid, sounds right. I tried it for a bit and gave up.
<Bitweasil>
There's an ARM version of that - it's even less well supported.
<geist>
yeha we've talked about it for fuchsia a few times, but there's a lot of work to make it go
<Bitweasil>
Why? You control a lot more of the stack than usual there.
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<cloudowind>
poor 16 bits got forgotten
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<gorgonical>
I come bearing complaints. This time, why does manually printing a single character to the serial port cause the rest of arm TF-A to suddenly work
<gorgonical>
I have bisected it to a specific point and I don't know why it works there
<mcrod>
UB
<gorgonical>
almost certainly
<gorgonical>
I mean I'm relieved that *something* makes the whole rest of it work suddenly
<gorgonical>
But disturbed also
<klange>
have you considered hiring an exorcist?
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<cloudowind>
yea but i think minumum 2 bits required to be able to say ive got a processing unit?
<heat>
its like, cool
<mcrod>
traumatic brain injuries aren't cool
<gorgonical>
i can think of a lot of reasons to not like tra
<gorgonical>
damnit beat me to it
<cloudowind>
theorically...
<geist>
heat: oh it's cool, it's just a pain for the kernel
<geist>
because now you have to be carefula bout addresses as they get passed in/out/etc
<gog>
hi
<cloudowind>
hello gog
<mcrod>
gog at work, we've had two thermal incidents, both causing smoke to appear and causing irreparable harm
<mcrod>
these incidents only happen when I put my hand on them
<mcrod>
tell me
<mcrod>
what's wrong
<mcrod>
and by "hand" I mean no computational intervention whatsoever
<gog>
your PWM phasing is backwards
<mcrod>
interesting
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<gorgonical>
This is wack yo
<gog>
hi gorgonical what's wrong
<gog>
oh a bug
<gorgonical>
Yes
<gorgonical>
I am seeing if inserting nops fixes it also
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<gorgonical>
Why is lowlevel development always like this
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<heat>
what
<gorgonical>
The important part of this little asm snippet seems to be the actual write to the uart device
<gorgonical>
Which is more disturbing
<heat>
what
<heat>
can you give out more details
<gorgonical>
If I add a 3-line inline asm to print a character to the console, the logging system of arm trusted firmware works
<gorgonical>
If I don't, it does not
<gorgonical>
I'm trying to figure out why this is
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<heat>
and nops dont fix it?
<gorgonical>
I have changed the snippet and it seems like the important part is actually the store to the uart address. Just setting the register values doesn't work
<gorgonical>
No
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<heat>
maybe TFA is borked? :/
<heat>
i don't know how that works exactly, though
<heat>
for ARM TF-A logging to work wouldn't it need to solely own the serial device? hence whatever is under it couldn't touch it?
<heat>
(brb rebooting)
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<gog>
heat why are you rebooting all the time
<gog>
heat
<gog>
HEAT
<cloudowind>
fresh air
<gorgonical>
The idea that the write to device works is strange
<gorgonical>
I
<gorgonical>
I've added 1000 nops to see
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<heat>
i am ack
<klys>
ack
<heat>
gog, cuz i went to play some vidya games with my friends on windoze
<heat>
now im back for more program
<gorgonical>
this is preposterous
<heat>
on linux
<gorgonical>
1000 nacks doesn't work but writing a single 'g' does
<gorgonical>
nops, whatever
<gog>
e
<heat>
E
<heat>
can you just share the serial port with TF-A like that?
<gorgonical>
I think each piece assumes the port has already been brought up
<gorgonical>
So as long as there's no concurrency they all cooperate. We're all still at el3 anyway I think
<gorgonical>
I am utterly perplexed
<gorgonical>
Writing to a random spot in memory doesn't work, but writing to the serial device after that makes it work again
<gorgonical>
It really is the shoving of a single character into the uart that wakes it back up or something