_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<MoeIcenowy> _florent_: I cannot imagine the adjust is so simple
<MoeIcenowy> My own lead to get the read latency -= 1 change (because there is RBURST (BURSTDET called by Lattice)), however for the write latency -= 1 I didn't find it (because I have no knowledge about the internal of LiteDRAM)
<MoeIcenowy> nickoe: not possible w/o proper primitives from Gowin
<MoeIcenowy> a primitive called GW_JTAG is known to exist in prim_syn.v in Gowin toolchain
<MoeIcenowy> but not documented at all
<MoeIcenowy> and GAO is surely encrypted
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<sensille> Hoernchen: the patch is only for the eth_clock. 30mhz is awfully low, where is the critical path?
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<Hoernchen> sensille, https://dpaste.org/BrVRK - apparently to a dpram? this is the unmodified "colorlite"
<tpb> Title: dpaste/BrVRK (Console/Bash Session) (at dpaste.org)
<sensille> 23ns routing, that is a long path
<Hoernchen> there are apparently some false paths that can be ignored - just, uh, knowing which ones are the false path is the problem
<sensille> do you need etherbone for your project?
<Hoernchen> i might, i didn't really plan to use a cpu, so it looks like the most obvious way to just have a bus
<Hoernchen> but i'm currently just trying to figure out what works and what doesn't work
<tpb> Title: dpaste/0jxuo (Plain Text) (at dpaste.org)
<sensille> colorlite.py --build
<sensille> (with 30mhz clock target)
<sensille> how do you call it?
<Hoernchen> literally like that
<sensille> with 50mhz: https://dpaste.org/q8Nq3
<tpb> Title: dpaste/q8Nq3 (Plain Text) (at dpaste.org)
<sensille> eth clk is hit and miss
<Hoernchen> can you ever got to 50?
<Hoernchen> get
<sensille> diamond can get to 50, but fails in the eth path. my patch might help there
<sensille> but 40 should be enough?
<Hoernchen> i guess so
<Hoernchen> i'm just wondering if there ever was a way to hit those default frequencies
<sensille> no luck with abc9/flow3 either
<Hoernchen> yeah i'm currently trying some of those magic ravenslofty cookbook incantations
<sensille> i don't feel well running a design with failed timings either
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<fts-tmassey> Hello!  I'm having trouble with linux-on-litex-vexriscv and a Terasic de0nano.  I've downloaded to the board, I get the side-to-side LED's, but I can't communicate with it.
<fts-tmassey> I think it's because I need to connect to a UART via the GPIO header pins, but I don't know what pins to use!  I'm happy to answer any questions I can, of course.
<fts-tmassey> I'm running on Debian Bookworm, with a Terasic de0-nano.  Quartus 22.1free.  I'm happy to provide parameters, logs, timings, etc. but you would have to help me to find these...  I basically followed the bouncing ball from the readme.
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<jevinskie[m]> <MoeIcenowy> "and GAO is surely encrypted" <- I’d bet we can get around that little road bump if that’s what is necessary for figuring out the primitive/enabling litejtag. ;)
<fts-tmassey> I have also successfully used Quartus to download a quick procedure from the Terasic manual.  Seeing as I see the LED's moving like I've seen in other tutorials, it seems I've successfully downloaded the FPGA code.  The problem is, I can't connect to the serial interface to download the Linux kernel, etc.
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<fts-tmassey> Here is an issue I've created with more details:  https://github.com/litex-hub/linux-on-litex-vexriscv/issues/348
<fts-tmassey> Thank you for any help you might be able to provide!
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<josuah> hello fts-tmassey!
<josuah> I'm not tinkering with linux-on-litex-vexriscv but with zephyr-on-litex-vexriscv (different devboard), but close enough :)
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<jevinskie[m]> For de0-nano try adapting this DECA board config that uses the onboard usb blaster 2 https://github.com/litex-hub/litex-boards/blob/master/litex_boards/prog/openocd_max10_blaster2.cfg
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<josuah> Did you have any plan for it?
<josuah> I thought about a board definition with a "null platform" of some kind that does not invoke any platform-specific primitive
<josuah> the top-level of LiteX would become a module in the user's design, with the bus exposed
<josuah> oh, I did not look, maybe that's already there in LiteX!
<josuah> _florent_: thank you for the merges by the way!
<josuah> We can work with a fork periodically synced with upstream for a long while, no pressure to merge anything :)
<whitequark[cis]> <MoeIcenowy> "and GAO is surely encrypted" <- what's GAO?
<whitequark[cis]> oh, Gowin Analyzer Oscilloscope IP?
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<whitequark[cis]> the use of GW_JTAG looks very straightforward to me, it's almost the same as the Xilinx one
<whitequark[cis]> btw the private keys to decrypt the Gowin IP are listed in plaintext, grep for "-----BEGIN RSA PRIVATE KEY-----"
<whitequark[cis]> if you wanna look at GAO IP write a few lines of openssl :p
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<josuah> whitequark[cis]: maybe they had bug when turning encryption off :D
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<whitequark[cis]> no it's just the implementation is like that
<whitequark[cis]> they're in the gwsyn.so library
<josuah> one would have to be in a country where reverse engineering allows as far as decrypting IPs to understand how the hardware works...
<josuah> even if the IP content is not included directly
<josuah> not sure how this all works to be honest.
<gurki> whitequark[cis]: thats hilarious, thanks for mentioning this :D
<whitequark[cis]> you just decrypt the IP and get done with it
<whitequark[cis]> don't tell me you've never pirated a movie either
<whitequark[cis]> it's no one's business what you do in the privacy of your own computer
<josuah> yes, but I did not write a novel out of the scenario of a pirated movie either
<josuah> if something needs to be integrated with open-source project for instance
<gurki> whitequark[cis]: im laughing about the plaintext key, not you doing whatever you do with it
<whitequark[cis]> yeah i was responding to josuah
<gurki> ah :)
<josuah> the question is about how to face a lawyer if that had to happen
<josuah> oh, nevermind
<josuah> if someone of the size of i.e. intel, nvidia wants me legally down, they probably do not need me to be actually stealing anything ^_^'
<whitequark[cis]> power does as power wants
<whitequark[cis]> though, i have once got a c&d from xilinx, and i'm still alive
<josuah> \o/ kudos on being alive, I mean it
<whitequark[cis]> you don't actually need to tell anyone where you know how to use GW_JTAG from
<Hoernchen> someone decrypts it and describes it, someone else implements it according to the docs
<whitequark[cis]> or you can always do a parallel construction, exactly the same thing as the state does when it doesn't want to give up sources of evidence
<whitequark[cis]> get it from RE, and then pretend you got it from very inspired experimentation
<whitequark[cis]> Hoernchen: I think this might not work in this particular case
<whitequark[cis]> since the person decrypting is still liable
<Hoernchen> in this particular case the "thing" is... not particularly unique or exciting, it should be reasonably easy
<whitequark[cis]> I mean
<josuah> I just understood all the 4chan leaks... someone needs it, someone "else" publishes it, it's out, grab it :S
<whitequark[cis]> I looked at GW_JTAG, I could describe it without any RE work
<Hoernchen> ah yes but: who is that person? imagine docs showing up somewhere...
<gurki> josuah: its a very, very (...) very complex topic with a lot of strong oppinions
<whitequark[cis]> I can trivially break Gowin encryption too but it's not enough of a challenge to bother
<josuah> gurki: sorry for opening the lid
<gurki> for me personally its a minefield im not touching with a long stick
<Hoernchen> the way it should not be done is the ham guys and their "reversed" ambe codec which is pretty much the dsp code decompiled and translated into c after running in the emulator..
<Hoernchen> that is just tainted beyond repair
<whitequark[cis]> as someone who thinks almost all IP should not exist I can only admire the degree of commitment there
<Hoernchen> ambe is a major issue, it prevents open source DMR because you're supposed to buy a physical chip to use it
<whitequark[cis]> yeah, I know about ambe
<Hoernchen> and i'm still trying to forget all the things i never saw while not looking at the nice lattice diamond text f.. uh.. binary blobs
<whitequark[cis]> i thought diamond ships ip as netlists?
<whitequark[cis]> and whatever the hell is that cursed simulation format
<Hoernchen> oh not the ip
<Hoernchen> the part and bit descriptions
<Hoernchen> long, long chains of boolean equations that tell you which bit does what
<Hoernchen> the lattice ip that is used by sinplify was rsa bsafe protected at the time, so.. slightly more difficult than grepping for the key
<Hoernchen> i.e. the tri speed ethernet mac
<whitequark[cis]> ahhhh
<Hoernchen> just found one of those pretty ascii tile maps
<Hoernchen> alld of that was such a long time ago.. 2012 or something like that
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