<MoeIcenowy>
btw for single chip ddr3 is write leveling not necessary?
<MoeIcenowy>
how does the DEL_VALUE on ECP5 decide the delay value when USER_DEFINED ?
<_florent_>
MoeIcenowy: For single chip, you can generally use static timings, that’s what’s we are doing on Artix7 (since no ODELAYs) , ECP5 and that’s what is done by some vendors (IIRC Efinix controller has an option for this to save resources)
<zyp>
aren't static timings orthogonal to the number of chips? even for a single chip you need the correct timings, and if you know the correct timings you could use static timings on a multichip system as well…
<MoeIcenowy>
I am still trying to dig out why the GW2DDRPHY ported from ECP5DDRPHY does not wotk
<MoeIcenowy>
work *
<MoeIcenowy>
I now start to think ECP5's DELAYG with p_DEL_MODE="DQS_ALIGNED_X2" is some magic
<MoeIcenowy>
but I cannot understand how this is implemented
<MoeIcenowy>
okay it looks like from the implementation of pack.cc in nextpnr, it's just a fixed delay value?
<josuah>
MoeIcenowy: is that possible that an instance from one device of vendor transposed to another device of another vendor works the same way at all?
<josuah>
oh... maybe you are trying to understand what exactly is portable and what is not, and hence try to guess what these parameters can be doing on one side
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<_florent_>
@zyp: sorry I was answering for write leveling case: with a single chip and without output delays, adjusting the clk phase and doing a few P&R is generally enough to get it working. For multichip, implementing proper write leveling requires output delays and proper calibration to find the timings. On a deployed and fixed design you can then use static timings but you’ll stil need a version of the design with the calibration to find them.
<_florent_>
MoeIcenowy: sorry, on my phone and don’t remember the details the GW2DDRPHY but we have also planned to work on it with @trabucayre in the next weeks.
<MoeIcenowy>
josuah: well yes true, and the major structure of them are both similar (and quite different with Xilinx ones)
<MoeIcenowy>
In addition I utilized the .vo files from the PnR tool (which will contain only primitives) to check how the vendor IP does
<MoeIcenowy>
and at least this can show what primitives are being used
<MoeIcenowy>
_florent_: BTW I cannot understand how is ECP5DDRPHY working -- it works at a so low frequency ...
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<josuah>
I thought ECP5DDRPHY was a primitive, but no, it's a LiteX class
<josuah>
MoeIcenowy: there is something called FPGA Libraries Reference Guide
<josuah>
which might have documentation for each primitive you can find in ECP5DDRPHY implementation