_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<nanoric[m]> Hello, I'm new to FPGA. Am I free to ask questions about FPGA here?
<sensille> nanoric[m]: i'm not the owner of this channel but i'd say it is quiet enough that you can. there's also ##fpga which is just general fpga talk with regular newbie questions
<nanoric[m]> Thanks!
<sensille> relevant here maybe up to page 10
<sensille> (and it is very inconvenient to have to click on a link to see your question, i'm on the irc side)
<nanoric[m]> sensille: Thank you for your recommand!
<sensille> my question would be, how do you know it is many clocks later?
<nanoric[m]> Because I can wait many clocks later to read it. Read operation is not eager.
<nanoric[m]> For example, I have a single to control the write from clock A, and another signal to control the read from clock B. The two signals are far apart in time.
<nanoric[m]> * in time(eg, 10 or more clocks).
<sensille> nanoric[m]: it should work (3 cycles should be plenty). the document might offer more solutions
<sensille> 5.6.1 resembles your solution
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