_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<nanoric[m]> sensille: thanks!
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<AndrewD> Anyone had success recently debugging vexriscv over etherbone in litex sim? litex_server dies with broken pipe when openocd connects for me, when following steps similar to https://github.com/enjoy-digital/litex/wiki/Use-GDB-with-VexRiscv-CPU
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