<MoeIcenowy>
_florent_: BTW I tried to tweak when dqs_re to be asserted, and the read leveling result seems better
<MoeIcenowy>
well it still doesn't pass read leveling...
<MoeIcenowy>
trying to deal with Python slicing is weird
<MoeIcenowy>
it behavior is so different to Verilog's
<MoeIcenowy>
_florent_: BTW on ECP5 is a high sys_clk needed for DDR to work ?
<MoeIcenowy>
I start to doubt 252MT/s is too slow for DDR3
<MoeIcenowy>
(but the timing of GW2A is quite bad ...
<MoeIcenowy>
even GW5A isn't something good
<MoeIcenowy>
well the JEDEC minimum is tCK = 3.3ns (300MHz clk) ...
<MoeIcenowy>
thinking about migrating gw2ddrphy to 1:4 instead of 1:2
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<_florent_>
MoeIcenowy: On ECP5 most of the targets are using 75MHz with DDR3 (so DDR 300) but it’s working fine at l’Eastwood down to 50MHz. trabucayre started adding 1:4 support so it could be worth exchanging together.
<MoeIcenowy>
_florent_: I did a quick try for 1:4 and then quick fail :-(
<MoeIcenowy>
300MT/s is also out of JEDEC spec (the JEDEC spec specifies at least 300MHz CK)
<MoeIcenowy>
BTW what's the meaning of "bus errors" of the DRAM controller?
<MoeIcenowy>
what does it mean when the bus error is now 0 but data error still exist?
<MoeIcenowy>
and for the read_latency of phy_settings, is it just used for a hint?
<MoeIcenowy>
BTW I start to doubt that the latency of the read codepath on GW2 is kinda like 9.5 sys_clks