<_florent_>
tpw_rules: With SDRAM, we indeed do not have automatic clock phase calibration, so this need to be adjusted from board to board (as you saw with your fix).
<_florent_>
tpw_rules: regarding memory inference, I would like to have proper memory specialization/generator in the future to be able to specialize for the architecture we are building for. For now we are just relying on the synthesis tool: Here is a N-KB memory, with M ports, please do your best with it :)
<_florent_>
somlo: strange for the failing variant. It however seems to be deterministic since you have 1/2 of data errors. This would be interesting to see if we also reproduce it in simulation with similar DRAM, if so, it will be easier to understand/fix
<_florent_>
somlo: This could be a Down/Up-Converter corner-case triggered by this variant.
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<somlo>
_florent_: both nexys_video and ecpix5 end up with a 128-bit wide LiteDRAM native port (they both have 512MB RAM, and use MT41K256M16 modules -- with "1:4" and "1:2" rates, respectively)
<somlo>
so the `d` in `fulld`, `linuxd`, `full4d`, etc. stands for 128-bit axi mem bus, specifically used on those boards to avoid width conversion
<RowanG[m]>
Could someone enlighten me regarding ECLKs in the ECP5 the lattice sysClock doc leaves me with questions...
<RowanG[m]>
So when a clock comes out of the PLL it's a PCLK. Currently I just use this PCLK in my design to also clock input/output flip flops and there doesn't seem to be an issue.
<RowanG[m]>
Now according to the PDF OP and OS also generate an ECLK.
<RowanG[m]>
How can I access it?
<RowanG[m]>
Or is that done "automatically" as in if use the OP/OS Clk it will use the ECLK for the IO flip flops?
<gatecat>
it's automatic if you connect it to one of the ECLK-connected ports
<gatecat>
I can't remember if that includes the IO ffs or just the 1:4/4:1 serialisation primitives etc that have an ECLK port
<RowanG[m]>
Thanks @gatecate
<RowanG[m]>
gatecat:
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<Guest11>
Hi, has anyone every got PCIe working with a Virtex 7 VC707 board?
<mikek_VA3TEC>
Hill all, I know this is embarrassing, I got Litex to compile with VexriscV for the Deca Board. But when I run lxterm I get this error... :(
<Guest11>
then "litex_term --speed 115200 /dev/ttyUSB0" should work
<Guest11>
but that board uses a JTAG-UART!? So you might need the "--jtag-name" parameter for litex_term, not sure though. According to the readme not. Correct USB port selected?
<mikek_VA3TEC>
So I am using the external serial... GPIO serial..
<VC707>
no anybody at all. The only thing that is working for me is the UART and DRAM
<VC707>
no PCIe
<mikek_VA3TEC>
same here
<mikek_VA3TEC>
which board?
<VC707>
VC707
<mikek_VA3TEC>
woah... that a big board
<mikek_VA3TEC>
5.2K?
<mikek_VA3TEC>
do you compile anything with it? did you look at the verilog code?
<VC707>
5.2€ ? Sounds about right but bought by the University
<VC707>
Yes I did, I also applied constraints from a Xillybus design that is known to work with exactly that board. I guess that made it worse, now it crashes the PC :D but before that, I only got 0xFF from the board
<mikek_VA3TEC>
what your Litex command line that you are using? you have the enable a lot of stuff I think..
<VC707>
I just need a fast way to transfer data from a host to the DRAM of the board
<VC707>
and back
<mikek_VA3TEC>
any jtag ports?
<mikek_VA3TEC>
you can run a GPIO at like 1Megabuad.. you just have to specify it in litex target file..
<VC707>
the xilinx_vc707.py has a "--with-pci" toggle but that is broken, after fixing it and other constraints, its generating the bit file
<mikek_VA3TEC>
cool... Did you do a pull request to Florent?
<VC707>
With the jtagbone it appears to be writing fast (about 10MB/s), but reading is super slow.
<VC707>
not yet
<VC707>
and sometimes it has timeout errors
<mikek_VA3TEC>
Ah cool Good, Did you calibrate the Ram?? mmight be something with that...
<mikek_VA3TEC>
again I am still learning...
<VC707>
that is done automatically, the DRAM works fine
<mikek_VA3TEC>
what do you get for a data rate? Around 10MB/s? just curious..
<VC707>
80MB/s read and write from the C app running on the default Virtex CPU
<mikek_VA3TEC>
oh yeah, I meant with Litex... are you able to do a calibration of the ram that way? or it's automatic...
<VC707>
the RAM calibration is done with a snippet of C-code that is provided by litex.
<mikek_VA3TEC>
and your Ram reads were good.... I am assuming... yup beyond me... Sorry wich i can help..
<VC707>
yes they work well, transfer with UART is also fine but slow (80KB/s)
<mikek_VA3TEC>
I am still struggling with getting a demo bin file to run... :(
<mikek_VA3TEC>
what speed did you connect with?
<mikek_VA3TEC>
115200?
<VC707>
950xxx
<VC707>
2M worked at some point but then stoppen working
<VC707>
I have a shorter cable now, maybe I try again
<mikek_VA3TEC>
yes.. ok good.. But with the higher bit rates i find the grounding and shielding is very important...
<mikek_VA3TEC>
yes...
<mikek_VA3TEC>
shorter cable and really good shielding and grounding..
<mikek_VA3TEC>
any EMI in the area will kill your data rate...
<VC707>
okay not the front USB ports, got it
<mikek_VA3TEC>
Also, if you can change your data rate but a few kilohertz you might be at a harmonic of power line... etc..
<mikek_VA3TEC>
or any inverters or switching power supplies...
<mikek_VA3TEC>
if you have a Spectrum analyzer around... see what's going in the lab.. but that''s a bit of overkill...
<mikek_VA3TEC>
for me I twist the TX amd RX together... but you may not be able to do that. depending on the cables..
<VC707>
I have just a regular USB cable
<mikek_VA3TEC>
hummm.... how are you changing the speed?
<mikek_VA3TEC>
what target file do you have?
<mikek_VA3TEC>
oh wait got it
<VC707>
--uart-baudrate 2764800 :D
<mikek_VA3TEC>
yup.. good try a little lower... 2764400 or 2764000... but at this point shot's in the dark..
<VC707>
I'll try, thanks
<mikek_VA3TEC>
where do you change the actual bitrate... I am trying to remember?
<mikek_VA3TEC>
i know that i chaned it in the target file...
<VC707>
2764000 and 2764800 are misses, I'll try 2764400 now
<mikek_VA3TEC>
These are just shot int he dark guesses...
<mikek_VA3TEC>
you can go a lot lower... 2Mb/s
<somlo>
_florent_: on second thought, it *might* have something to do with width conversion. I built a `linux` (64-bit memory axi port, which would have to be up-converted to the 128-bit liteDRAM port) -- memtest passed, kernel booted, but I started getting weird errors communicating with the sdcard
<somlo>
then I built a `linuxq` (256-bit memory axi port, which needs to be down-converted to the 128-bit liteDRAM port -- this is on a nexys_video)
<somlo>
here I got a failing memtest, never made it to booting linux
<somlo>
anyhow, I'll update issue #1432 so there's a record of all this experimentation :)
<somlo>
I wonder if I can find an older (pre-AXI-overhaul) commit in LiteX that still builds (might run into trouble failing to find a matching point-in-time commit for all the other bits and pieces, like litedram, litesata, litesdcard, etc.)
<somlo>
... and bisect from there
<somlo>
the advantage of having a single repo with lite[sata|dram|sdcard|etc.] in subdirectories might be that one can have a much easier time bisecting for regressions
<somlo>
since those bits are in separate repositories, it's hard "synchronizing" while jumping around in the main litex repo during a bisect
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<nickoe83>
I just build a pmod for usb to work with the kwargs["uart_name"] = "usb_acm" i.e. the valentyusb.usbcore. It appears to work great, but when I do reboot in the serial console it will not reconnect? Why could this be?
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<nickoe>
Ok, on better nick now..
<mikek_VA3TEC>
How many nick are there? :)
<nickoe>
one true only me :)
<mikek_VA3TEC>
36 or 83 of you! :)
<mikek_VA3TEC>
I am trying to upload a kernel.bin file but it keeps failing...
<mikek_VA3TEC>
do I have specify the speed every time??
<mikek_VA3TEC>
well demo.bin
<mikek_VA3TEC>
I am using litex_term..
<mikek_VA3TEC>
CRC error
<nickoe>
Hmm, on my other computer it does appear to work ok. I use tio for the terminal.
<nickoe>
mikek_VA3TEC Is it over uart?
<nickoe>
The default should be 115200 IIRC
<mikek_VA3TEC>
well GPIO uart
<mikek_VA3TEC>
I get the Litex> prompt.
<nickoe>
If using something other than 115200 you may need to specify it
<mikek_VA3TEC>
Memspeed at 0x40000000 (Sequential, 32.0MiB)...
<mikek_VA3TEC>
Write speed: 15.6MiB/s
<mikek_VA3TEC>
Read speed: 22.1MiB/s
<mikek_VA3TEC>
litex>
<tpw_rules>
the litex memory access speed always seems kind of bad. is that just limited by the cpu then? i hope the caches would enable better bandwidth
<mikek_VA3TEC>
Well it's the MISTER External ram. I had to lower the clock rate to times 1... instead of X2. I was getting errors.
<tpb>
Title: #litex on 2021-07-23 — irc logs at libera.irclog.whitequark.org (at libera.irclog.whitequark.org)
<mikek_VA3TEC>
is LiteDRAM separate from litex-boards?
<mikek_VA3TEC>
Thanks!
<leons>
Yes, all modules are split into different repositories. LiteX just contains the basic infrastructure and code to glue things together along with CPUs and basic peripherals, litex-boards is essentially a collection of SoC instantiations fit for a selection of different boards, with appropriate constraints
<mikek_VA3TEC>
Any Document ion on how to build LiteDRAM and then accessing it with litex-boards? I will start by looking at LiteDRAM.
<tpw_rules>
sdram does not have a calibration routine
<mikek_VA3TEC>
ok
<tpw_rules>
leons: hi?
<tpw_rules>
thank you for that link
<tpw_rules>
i didn't think the vexriscv would be that slow with cache but i guess we will find out
<mikek_VA3TEC>
Ah ok, I found where it has the SDram hardware.. sdrphy_mod = {"xs_v22": W9825G6KH6, "xs_v24": AS4C32M16}[mister_sdram]
<mikek_VA3TEC>
Line 129...
<mikek_VA3TEC>
But mine is version 2.5 have to get the microscope out to read the chips.. :)