<somlo>
that said, it still fails dram initialization. Which is a strange coincidence, because `fulld` (128-bit wide memory bus with fpu) also fails dram initialization on the nexys_video (different board, different toolchain, same cpu verilog)
<somlo>
which makes me wonder if there's something broken about just the verilog for that particular variant (other variants of the same width work fine on both boards -- I can try more cores or drop the fpu and it's fine on nexys_video; I can only drop the fpu on ecpix5, but that's fine too :) )
<tpw_rules>
i had some dram init failures when fooling around yesterday on cyclone v and was able to fix it by tweaking the clock phase. but my ram is boring old sdram
<tpw_rules>
that same fix and comment is present on a lot of boards
<somlo>
this is litedram failing to "train" (read/write leveling) when the SoC is built with a very specific variant of rocket cpu (fpu-enabled, 128-bit wide memory port, single-core)
<somlo>
any other cpu of the same family (4-core, or single-core without fpu), same memory port width, works just fine
<somlo>
I'd prefer to find a way to tweak LiteDRAM or the leveling software initialization if possible -- digging into how the cpu is different from its brethren is *hard* (requires understanding Chisel :))
<somlo>
so I'd prefer to do that only if nothing else works first :D
<tpw_rules>
it seems quartus is unable to infer Migen RAMs
<tpw_rules>
sometimes
<tpw_rules>
is there a way to like increase the verbosity?
<tpw_rules>
when quartus doesn't infer it it doesn't even mention it
<tpw_rules>
oh, it's dependent on the size. amazing