06:36 <_florent_> leons: sure, that's good to have these conversation/feedback since requirements for the deployment can be different. Current tools were mostly here to simplify development and working with upstream, but I also need to be able to deliver collection of validated LiteX packages to clients.

06:37 <_florent_> leons: BTW, a freeze feature has been added recently to litex_setup.py (./litex_setup.py --freeze), this generate a git_repos dict that can be re-integrated in litex_setup.py to install/use a fixed collection of packages.

06:38 <_florent_> leons: --tag also allow you to install the collection of packages of a specific release (ex --tag=2022.08 for the last release)

06:39 <_florent_> leons: but that's still some custom solutions, I've also planned to allow pip use for install, so if you want to handle nix, things should be in a better shape :)

06:40 <_florent_> somlo: nice for Fedora! Even with the crash, that's a nice first step.

06:44 <_florent_> tnt: yes, the error message are indeed obscure, error message on LiteX SoC part have been improved (but there are still lots of improvement to do), improving error message on the HDL generation will also have to be done in the future

06:46 <_florent_> tnt: Regarding your error message, do you have more information on what you are implementing? If you provide a minimal repro, I could have a look

06:51 <tnt> _florent_: that vivado message was when trying to build a 2048x256 SyncFIFO but the thing is I used that same fifo instanciation somewhere else and it worked fine there, so I'm guessing it's something in the "surroundings" that makes it go crazy.

06:52 <tnt> (and I was actually hapilly surprised it was using UltraRAM for that FIFO in the case where it worked)

06:53 <_florent_> tnt: Ah OK, just in case, setting buffered=True could also ease things for BlockRAM inference

06:56 <tnt> Yup, I did use buffered=True

11:44 <tnt> _florent_: so it refuses to synth it when I connect the input of the sync fifo to the output of a small async fifo.

11:45 <tnt> That's the snippet : https://pastebin.com/S7j0TSUc

11:45 <tpb> Title: cdc = AsyncFIFO([("data", 256)], 32, buffered=True) cdc = Clock - Pastebin.com (at pastebin.com)

11:46 <tnt> I wired the input to some random counter so it's not linked to the rest of the logic. If I put that generator in self.sync.radio and connect it to the 'cdc' fifo, it fails. If I move the generator to the self.sync (sys) domain and remove the cdc fifo entirely, it synth fine.

12:12 <tnt> Arghhh ... I think fifo.sink.connect(cdc.source) should have been cdc.source.connect(fifo.sink)

12:13 <tnt> I thought this was commutative and didn't pay attention to the direction

17:33 <slagernate> well, after too many struggles, it looks like I'll be reverting back to writing systemVerilog and using Lattice's SenseAI tool instead of trying an SoC with CFU (using a Lattice CrosslinkNX FPGA). Unless someone can share a demo project that works with the CrosslinkNX eval board?

17:42 <slagernate> prjoxide not working and my radiant tool giving the following error: `@E| Mal-formed command line - please check for extra ` `quotes in macro specification'

17:46 <slagernate> Maybe I can still have some fun and simulate my testbenches with migen/amaranth..

17:54 <slagernate> even the icebreaker (based on the lattice ultraplus fpga) didn't fully work for me:(  https://github.com/icebreaker-fpga/icebreaker-litex-examples/issues/11

18:56 <nickoe> :/

19:28 <nickoe> Hmm, does there exist any litex compatible camera MIPI IP?

21:39 <mithro> People here might be interested in a recent presentation that Antmicro did at the ESSCIRC workshop about "Pre-silicon testing of SkyWater MPW designs using co-simulation with Renode and Verilator" found @ https://docs.google.com/presentation/d/e/2PACX-1vT2pOMi-crvIhns7ulGvmvDdFy7pGb0L28kJouSnseVHl4fHugabSz5yLD5ocU7CfaTtNVSWDyJwl9b/pub?start=false&loop=false&delayms=3000

21:40 <tpw_rules> "You need permission to access this published document."

22:18 <mithro> Sorry, that URL should have been https://docs.google.com/presentation/d/e/2PACX-1vT8OYu5lkpaHLJeBu07BFR-3u88vtRHOnKsIBAVSk4gLCa3-GaDWUny1XQ_rEJxaMJgl6LbmtbBXayc/pub?start=false&loop=false&delayms=3000

22:18 <tpb> Title: [public copy] ESSCIRC workshop 2022 presentation [shared] - Google Präsentationen (at docs.google.com)