09:38 <DerekKozel[m]> Is there a way to have the registers of the PCIe interface stable between rebuilds if the PCIe gateware isn't changed? I'm trying to minimize the number of times the kernel and userspace drivers need to be rebuilt when there aren't changes to that area of the SoC.

09:48 <tnt> DerekKozel[m]: you can fix the address of the "top level" blocks (i.e. the ones directly under the SoC).

09:51 <tnt> DerekKozel[m]: https://pastebin.com/UTriYnj5

09:51 <tpb> Title: class BaseSoC(SoCCore): csr_map = { 'ctrl' : 0, - Pastebin.com (at pastebin.com)

09:51 <DerekKozel[m]> Thanks!

09:52 <tnt> Now inside those blocks there is (AFAIU) currently no way to manually define a memory map ... (which is annoying TBH because when you want to pre-plan for future extension or multiple configs havign compatible memory maps, you'd need that)

09:54 <DerekKozel[m]> That's a start at least. Right now as long as the interface is stable between rebuilds and minor changes of the same design that's sufficient

20:33 <_florent_> tnt: that's indeed a current limitation that I should remove (this would allow me to remove some ugly workarounds I have in some designs to keep a fixed memory map...). It's probably not complicated to implement, I'll try to have a look at this soon.

20:39 <DerekKozel[m]> The more stable the register map can be the more feasible it gets to do things like have packaged drivers for the CLE-215, or at least reduce it to a rare build/upgrade.

21:38 <cr1901> Did there used to be a wishbone CDC verilog file provided with LiteX?