_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<mithro> People might find this project interesting -> https://github.com/google/silifuzz
<tpw_rules> mithro: pm?
<mithro> ?
<tpw_rules> do you mind if i talk to you over private message briefly?
<mithro> tpw_rules: Sure
<mithro> It would probably be awesome if someone would see if it is possible to get silifuzz connected up to LiteX & Verilator based simulation....
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<nickoe> Hmm, can someone refresh me. Why don't I see my module in the sim output when I have added with as         self.submodules.mymod = MyModule(platform, sys_clk_freq) ?
<nickoe> If I break on Builder, and inspect my soc object I do see it listed as soc.mymod ...
<nickoe> I only see TOP.sim.FemtoRV32 in the gtkwave device tree
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