_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tnt> Mmm ... just updated litex and now it doesn't want to build riscv stuff :/ "ERROR: Compiler riscv-none-embed-gcc can not compile programs."
<tnt> "unsupported ISA substring '2p0_m'" err ...
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<tnt> nm. Looks like 8.2.0 wasn't good enough anymore. But 12.x works.
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<cr1901> the rv extension situation is... bad
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<tnt> Yeah. And looks like the ROM grew again, doesn't fit anymore in the 8k I have allocated :/
<tnt> I just need it to train the DDR4, why does it need 11k of code to do that ..
<tnt> err sorry, it has 32k already and doesn't fit in that
<tnt> Is there a way to supply custom cflags to build the bios ?
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<josuah> hello! I am wondering how the UART<->Wishbone bridge works, does anyone know where the wire protocol is described?
<josuah> I think it is named UARTBone
<josuah> and I cannot tell whether it has anything in common with https://wishbone-utils.readthedocs.io/en/latest/wishbone-tool/
<tpb> Title: wishbone-tool - All-in-one Wishbone Binary and Library — wishbone utils 0.7.7-1-gfc2d1a0 documentation (at wishbone-utils.readthedocs.io)
<josuah> ok, so this commit https://github.com/litex-hub/wishbone-utils/commit/644446f9a372d77a0a6279d51901770b06e80b03 suggests that Xobs is the author of LiteX of spibone and uartbone in addition of wishbone-utils
<josuah> it looks like everything dealing with wishbone-tools is in xobs hands, including attemps to make it go on Fomu.im... I'll get to reach Xobs then :)
<josuah> o/
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