_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<shenchen> i'm working on a small vexriscv+eth+sdram system with litex_sim, using stock bios and tftp booting. the demo app boots up fine, small changes to demo works too.
<shenchen> however, the instance i added eth_init() to the demo app's main(), it no longer boots.
<shenchen> what's baffling to me is that if i copy the code of eth_init() to my_eth_init() in main.c, it boots. objdump tells me that my_eth_init() and eth_init() are exactly the same in assembly code.
<shenchen> i'm wondering if there is some compile/link options i need to extend the demo app, that i overlooked?
<shenchen> TIA
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<HansM> Hi, I'm am curently playing with the PCIe stuff (Xilinx VC707). I want to read/write data from the host into the DRAM. I have followed the advice in [1] to add a host AXI MMAP component and an SoC region (to be mapped into the host), but I have no clue how the host part should look like.
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