07:31 <tnt> Shouldn't the PCIe address translation be handled by litex_server rather than the client ?

07:32 <tnt> After all, it's kind of its job to fully abstract the access method from the client so having them check if the server uses PCIe and apply the offset is kind of weird.

07:33 <tnt> (And also requires updating the clients ... like for instance https://github.com/litex-hub/wishbone-utils/tree/master/libeb-c knows nothing about it)

13:57 <somlo> gatecat: I finally managed to build a fpu-enabled rocket + litex on the ecpix5, which passes timing, and memtest, and boots linux via opensbi. Thanks again for pointing out "flow3" -- I had to run nextpnr a few times in a loop until it managed to pass timing, but eventually I got there :)

13:57 <gatecat> very nice :3

13:58 <gatecat> another thing to play with might be `--tmg-ripup` with nextpnr

13:58 <somlo> now that I have it working, let me try booting fedora on it

13:58 <gatecat> it's sometimes helpful when designs are just failing timing

13:59 <somlo> oh, interesting -- I'll have to play with that flag too (and add it to the litex command line in case it proves helpful :)

14:02 <somlo> but the main thing is I can finally leave BBL behind (and unfortunately the versa board, which doesn't have room for the fpu on its 45k ecp5 chip)

14:06 <tnt> BBL ?

14:19 <somlo> tnt: https://github.com/riscv-software-src/riscv-pk (the "old thing" that used to handle m-mode, before opensbi)

14:20 <somlo> notably, it had the ability to emulate trapping fpu opcodes on a cpu that didn't have it in "hardware"

14:20 <somlo> which is something opensbi refuses to implement :)

14:58 <esteves> Hello everyone, good afternoon, I was looking at this tutorial (https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers#memory) and I need to do another config that is not listed, Wishbone rw, logic w. Can someone guide me on how to perform this?

15:05 <zyp> > Basically, you’re allowed just one write port without also inferring an arbiter. Although the RAMB36E1 primitive supports two write ports, the verilog template used to infer them is rejected by Vivado (as of 2018.2).

15:07 <zyp> so you can either put an arbiter in front of a single ported memory or directly instance a dual port primitive

15:11 <esteves> so, I would have to use directly the wishbone interface in the logic to write to the memory? or there is already a module doing the abstraction?

15:19 <tnt> Oh really it doesn't support the pattern ? That's a shame :/

19:04 <somlo> so fedora booted all the way to `login:` on the ecpix5 as well (http://mirror.ini.cmu.edu/litex/fed_ecpix5_1.log), very similar to the way it went on the nexys_video (http://mirror.ini.cmu.edu/litex/fed_1c_2.log)

19:04 <somlo> at this point I think it's probably in the software

19:05 <somlo> I'll try it on the trellisboard and the genesys2 (1G RAM, less memory pressure), and maybe try turning off a buch of the on-by-default services