_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<likewise> Is it correct the litex-boards/litex_boards/platforms/*.py files do not have the executable flag?
<likewise> Problem I have with the quick start is nothing happens when I run: python ./xilinx_alveo_u250.py
<_franck_> likewise: platform files are meant to be used by target files (or your own file)
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<likewise> _franck_: Thanks, I see my noob error now.
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<likewise> Does Litex support building an SoC as a stand-alone (set of) Verilog source(s), i.e. for re-use in RTL projects? I am interested in building a VexRiscv with AXI4 Crossbar and a AXI->AXI4Lite converter with AXI4 Lite cross bar. I could use some help, if anyone is interested in a code bounty, let me know.
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<_florent_> likewise: That's one of the next task/priority in my todo list :): Create a generator to generate the SoC as a standalone core (as we are already doing with LiteDRAM/LiteEth, etc...)
<_florent_> to generate a standalone verilog core similar to this ^
<_florent_> the user will be able to customize it with most of the parameters exposed on targets (and probably some others). I should start this next week and could be interested to have someone testing it and providing feedback
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<cr1901> _florent_: If you decide to use a different HDL going forward, does that mean LiteX will support two different (or more!) languages, or will the cores be rewritten to a single HDL eventually?
<_florent_> cr1901: 1) first experiment/mature it on a new/independent design 2) offer a full Migen/LiteX compatibility layer and test it on actual LiteX design 3) Switch progressively :)
<shorne> ah, I just spend a week (hour here, hour there) trying to figure out why my platform is unstables, kernel crashing in a very strange spot that makes no sense
<shorne> I tried bisecting the kernel, toolchain, litex, what else!
<shorne> Finally I remembered (and doing some git reflog snooping) I updated the mor1kx core earlier this month, it turns some changes we did last year for formal verification I haven't been running with.. it seems that broke something
<shorne> rolling back mor1kx to around 2021 Feb fixed the instabilities