00:44 <jevinskie[m]> Ah, I may have found the issue. florent am I correct that I can't just use add_wb_slave() to add a 2 bit wide WB bus (converted from 2 bit wide addr Avalon-MM bus) to the 30-bit wide SoC WB bus? Do I need to do the address decoding myself?

00:58 <jevinskie[m]> Hmm, WB's cyc lets me know if I'm selected

07:17 <_florent_> jevinskie[m]: you use self.bus.add_slave, similar to this https://github.com/enjoy-digital/litex/blob/8ac3fbc0391b133775cbb6f12db89a27d7b18bd4/litex/soc/cores/led.py#L103-L107

07:18 <_florent_> LiteX will do the address decoding itself

07:19 <_florent_> jevinskie[m]: BTW, for these kind of integration/tests, litex_sim can be very useful with Display (printf equivalents) in your code, ex: https://github.com/enjoy-digital/litex/blob/53750715d7ad23f14a75b97f8d0592aa63839862/litex/soc/cores/uart.py#L298

07:21 <_florent_> jevinskie[m]: simulation waveforms are nice, but you still have to search things that are interesting in it. Display has the advantage to automatically print the information you want on a specific event when running the simulation

09:35 <shenki> _florent_: hey, are there common causes of the bios crc failing?

09:35 <shenki> i have it failing in both sim and on the arty with microwatt

11:28 <yrrapt[m]> Hi all, I am trying to create a SoC with a custom VexRiscV configuration. I create the verilog for the core using the VexRiscV repo but I can't figure how to configure LiteX to use my new source, it seems the variants are fairly hardcoded into LiteX at the moment.

11:28 <yrrapt[m]> Does anyone have any advice about the best to use a custom config?

12:40 <zyp> yrrapt[m], https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/vexriscv/core.py#L356

12:57 <yrrapt[m]> @zyp thanks, that seems to work.

22:20 <jevinskie[m]> Finally got it working for the simple gpio avalon. I thought I was using add_wb_slave wrong but it turns out I was missing a hex 0 in my test code for the MMIO addr. Doh! I don’t understand why I need to register the outputs but if I don’t the read data arrives a cycle too soon (since the main decoder is registered) https://github.com/jevinskie/litex/blob/1ac16114bb220542134cae96229bc9eedecff09d/litex/soc/interconnect/avalon.py#L86

22:20 <jevinskie[m]> I thought the bridge would be independent of the decoder registered mode…