Ah, I may have found the issue. florent am I correct that I can't just use add_wb_slave() to add a 2 bit wide WB bus (converted from 2 bit wide addr Avalon-MM bus) to the 30-bit wide SoC WB bus? Do I need to do the address decoding myself?
Hmm, WB's cyc lets me know if I'm selected
jevinskie[m]: simulation waveforms are nice, but you still have to search things that are interesting in it. Display has the advantage to automatically print the information you want on a specific event when running the simulation
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_florent_: hey, are there common causes of the bios crc failing?
i have it failing in both sim and on the arty with microwatt
Hi all, I am trying to create a SoC with a custom VexRiscV configuration. I create the verilog for the core using the VexRiscV repo but I can't figure how to configure LiteX to use my new source, it seems the variants are fairly hardcoded into LiteX at the moment.
Does anyone have any advice about the best to use a custom config?