_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> jevinskie[m]: From what I remember from Avalon (MM and ST), I indeed remember scratching my head on latency issues. This is really not intuitive and and you often have to introduce stupid logic for that in the code.
<_florent_> for ex, that's what does the subset of Avalon-ST present in LiteX: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/avalon.py#L15-L20
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<_florent_> sajattack[m]: I still need to validate the ECP5/Artix7 Link on the Acorn Baseboard. Once done, it should be possible to produce some when components will be available...
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<ilia__s> _florent_: do you want me to prepare this link test? should not take too long