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<Leon[m]>
Is there anything I need to watch out for when changing my SoC's clock frequency? I'd like to go down from 100MHz to 10MHz, and while the rest still works my Gigabit-LiteEth link doesn't seem to work anymore. My CRG is setup up similar to how it's done in digilent_arty.py. I didn't expect this to influence the Ethernet clocks too much given they are generated based on the RX clock, right?
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<zyp>
leons, I would guess that the data path is not wide enough to sustain the data rate where it crosses over into the 10MHz domain
<zyp>
e.g. if you're pushing gigabit data through a 32b wide stream, you can expect it to work down to 31.25 MHz
<leons>
zyp: ah, yes, that makes sense! thanks for the explanation.
<leons>
Is there a better method other than trial and error to see which clock frequencies work out? :)
<leons>
I tried a buch. Sometimes LiteX can't find a suitable CRG config, other times Vivado complains, sometimes I get a bitstream but it doesn't work :)
<leons>
I have my SoC working at 125MHz, but that's about it :)
<zyp>
knowing how stuff fits together help, I don't know your setup :)
<zyp>
suitable CRG config is probably a matter of finding a valid combination of PLL factors
<zyp>
other than that I guess it's a combination of how fast each domains needs to be, and how fast each domain is able to meet timing
<leons>
zyp: fair, that's what I suspected.
<leons>
I wouldn't want to bother you with details of my setup, it was a more general question I suppose
<zyp>
if you know the data rates and widths (and buffering strategies) of the streams crossing domains, you can determine how fast they need to be to work
<zyp>
e.g. if you have a fast domain feeding into a slower domain, the slow domain either needs to have a wide enough data path to still handle the full data rate, or the fast domain needs to have enough buffering that it's enough to handle the average data rate
<zyp>
or you could have flow control, in which case the slow domain would apply backpressure when it can't keep up
<Melkhior>
leons: depending on your FPGA, you may want to use separate PLLs to generate unrelated clocks
<leons>
zyp: right, makes sense. It's obvious when you think about it, but I've never really tweaked the system clock or done clock domain crossing, so I've been wondering why setting the parameter to certain values causes things to not work any longer :D
<Melkhior>
leons: you can also add 'margin=0' as a parameter to create_clkout, this will force the algorithm to search for a closer match (by default it seems to try to run the PLL as fast as possible)
<Melkhior>
(so sometimes it cannot find an exact divider)
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<OmkarBhilare[m]>
Hi _florent_ ,
<OmkarBhilare[m]>
I have generated litedram core with standalone generation, on ICE40HX8K I tried with serv + sdram, but the ICESTORM RAM is not enough.
<OmkarBhilare[m]>
So I also generated the litedram core with CPU as none, just wanted to ask about the initialization part.
<OmkarBhilare[m]>
Do I need to run these all steps first?
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<chiefwigms>
hey _florent_ - i finally got a uart host bridge (had to order a pmod uart since all the gpio on the board is pmod) up and running. how would I check the tx/rx freqs? (you mentioned a simple counter in the clock domains), but i'm not sure how to do that