_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<david-sawatzke[m> alainlou: FYI, I've found an example for storing the bios in the external spi flash: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/muselab_icesugar.py
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<_florent_> mithro: Scalenode seems interesting, I also bought some hardware some time ago to build to create a local regression bench but haven't set it up yet
<_florent_> Melkhior: Nice, thanks for sharing
<Melkhior> _florent_: thanks for Litex :-)
<Melkhior> BTW for the cheap DECA board, there's a controller now: https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/
<tpb> Title: BrianHG_DDR3_CONTROLLER open source DDR3 controller. - Page 1 (at www.eevblog.com)
<Melkhior> version 1.0 should land soon
<alainlou> thanks david-sawatzke[m! I'll need to have a look!
<alainlou> happy sunday everyone! sorry to disturb but I'm kinda stuck on a problem and would appreciate any help! https://github.com/litex-hub/litex-boards/issues/253#issuecomment-903301915
<Melkhior> alainlou: looks like a speed mismatch, but I guess you already double-checked the settings on lxterm ? (as you've clearly checked on the UART size!)
<Melkhior> you might want to try minicom just to be sure
<Melkhior> s/size/side/
<alainlou> hey Melkhior, thanks for the tip - yea unfortunately I get the same problem :(
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<jevinskie[m]> What’s the name for the ddr3l mode where everything is done single data rate?
<tnt> slow ?
<Wolf0> _florent_: nice! thanks!
<Wolf0> I've tried it on four FPGAs so far, three boards (one board is dual-FPGA)
<Wolf0> Only one of them takes 1200Mhz on the HBM2. :3
<jevinskie[m]> tnt: yeah but also perhaps simpler and lower latency :)