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<promach[m]>
<promach[m] "and what do you mean by DRP inte"> _florent_: may I know if litedram is using DCM_SP or PLL_BASE settings for spartan-6 ?
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<_florent_>
tnt: Congrats for Linux on iCE40, great work! Similar to your Doom port, I'm not sure the iCE40 designers were expecting this with their chip :)
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<tnt>
_florent_: Thanks :) Yeah, I'd love to see the iCE40 designers reactions ! For the doom port at least it was more reasonable and the speed is basically what I had to play back in the day on my not great 486. Here, it's pushing it a bit more so usefulness beyond demo is meh. But it shows you can do a lot with little if you try hard enough.
<tnt>
(And also, more importantly, this should settle once and for all "I wonder if you could run linux on it" questions)
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<_florent_>
tnt: I also really liked your work on Doom, this a very good way to show that if you do things correctly and put enough efforts to it, lots of things are possible even with small FPGA!
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<OmkarBhilare[m]>
_florent_: thanks for the link, I have exposed the wb bus in my litexcore and also configured that wb bus to other logic of my code.
<OmkarBhilare[m]>
Just wanted to ask one thing if serv is initializing the SDRAM IP then on wishbone bus we can directly read or write, right?
<OmkarBhilare[m]>
(basically on wb bus do we need to do any initialization part?)
<OmkarBhilare[m]>
* florent: thanks for the link, I have exposed the wb bus in my litexcore and also configured that wb bus to other logic of my code.
<OmkarBhilare[m]>
Just wanted to ask one thing if serv is initializing the SDRAM IP then on wishbone bus can we directly read or write, right?
<OmkarBhilare[m]>
(basically on wb bus do we need to do any initialization part?)
<_florent_>
OmkarBhilare[m]: Once the SDRAM is initialized by your CPU, you can access the SDRAM from the Wishbone bus as a classical MMAPed peripheral