<_florent_>
And then create CSR register in the design to probe value of internal signals (or just add a LiteScope instance)
<_florent_>
for the KU/1000-baseX support, the first thing to look at are the initialization FSM, be sure that TX and RX are initialized correctly
<_florent_>
then check the TX and RX frequencies (can be done with a simple counter running in TX/RX clock domains connected to a CSRStatus that is monitored every second through the bridge)
<_florent_>
Sorry I've not been able to spend time on this yet, too much things to do :)
<chiefwigms>
k
<_florent_>
OmkarBhilare[m]: For LiteDRAM standalone generation, it's not possible to control the data_width of the wishbone control interface
<_florent_>
initial support has been added for user port data width, but it will probably only be available for the native interface
<_florent_>
(for now)
<OmkarBhilare[m]>
<_florent_ "initial support has been added f"> Okay thanks
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<geertu_>
Anyone else seeing random corruptions with current litex-rebase?
<geertu_>
The /etc/init.d/ scripts fail with weird errors
<geertu_>
cat'ing the files show they're fine
<geertu_>
executing them with "sh -v" shows the messed up content.
<geertu_>
An older version based on v5.13-rc5 works fine, so I'm bisecting...
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<somlo>
geertu_: I am getting occasional invalid opcode kernel oops on rocket, but tracked it down to what is most likely timing failures in the ecp5 bitstream -- rebuilding the bitstream made the kernel stop crashing
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<somlo>
no idea what your underlying "hardware" is, but maybe rule that out first, before bisecting?
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<blackpepper>
After talking to somlo yesterday, I created a Fedora VM to try linux-on-litex-vexriscv. Now I am finally able to get "litex>" prompt at simulation. Thanks somlo for leading me to switch to Fedora!
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<blackpepper>
Now a question -- Does the simulation accept user keyboard input at "Litex>" prompt? Right now my simulation seems frozen at "Litex>" prompt.
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<somlo>
blackpepper: if everything goes well, you should be able to interact with your simulation via the prompt (sorry, can't help you any further, not a vexriscv user, and don't have access to my litex stuff at the moment)
<somlo>
blackpepper: also, unrelated to anything, you're disconnecting and re-connecting to this channel about once every 2 minutes -- just FYI :)
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<geertu>
somlo: we'll see...
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<blackpepper>
Thanks for letting me know I'm disconnecting at this channel. I'm using https://web.libera.chat/gamja/. I will search around how to keep connected to this channel.
<somlo>
so, unlike me, you found a bona fide regression...
<geertu>
somlo: You're using 64-bit rocket, right?
<somlo>
yeah
<geertu>
I knew it was working fine on my beagleV, so my first guess was an rv32 issue
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<tcal>
@xobs, mithro mentioned you might have created a way to easily specify a custom Vexriscv build, integrated with a Litex build? I know how to do one-off experiments by modifying the pythondata-cpu-vexriscv Makefile and/or the top sbt script and rebuilding a specific variant, or also how to add a new variant, but did you have another way?
<somlo>
gertu: I assume this will go away eventually (hopefully soon) if I keep rebasing the litex-rebase branch...
<somlo>
i.e., whatever fix for this regression will get applied upstream, and pulled into litex-rebase from there
<geertu>
somlo: Yep, I assume it will be fixed quickly upstream