02:14 <jevinskie[m]> I’m making progress on adding jtagphy/primitive support for altera. I’m battling some off by one bug now but it’s otherwise working like my toy example with Xilinx jtag. No altera virtual jtag bs either, just standard usercode passthrough :)

08:24 <_florent_> jevinskie[m]: nice, hoping you won't spend too much time on this last"off by one bug"... Are you planning to integrate it with LiteX? With litex_term or JTAGBone?

13:47 <chiefwigms> hey _florent_ - any luck?

14:22 <jevinskie[m]> Yes, with jtagbone and by extension litex_term (should be a lot faster than the virtual “Atlantic jtag” UART.

14:22 <_florent_> chiefwigms: sorry, no yet

14:22 <chiefwigms> any tips on what to try to debug?

14:22 <_florent_> jevinskie[m]: great! The JTAG UART over Atlantic debug is indeed a very slow

14:24 <_florent_> chiefwigms: the first thing would be do to a review of the parameters, then check the clocks/init (verify the clock frequency are the ones expected, that the transceivers are initialized correctly) and then look at the RX/TX data to with a Logic Analyzer

14:24 <_florent_> (can be done with LiteScope in our case)

14:24 <chiefwigms> gotcha