<leons>
On an UltraScale+ board I'm trying to support, I'm getting an error that `sys_rst` is driven by both an FDPE primitive, as well as some logic of the CRG IDELAYCTRL on latest LiteX master.
<leons>
ERROR: [Synth 8-2576] procedural assignment to a non-register sys_rst is not permitted
<leons>
Thanks, that works! I tried to be clever and not just copy everything verbatim from kcu105, but it turns out that's exactly what's necessary :)
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<leons>
Awesome, the first board where I got the DRAM to work completely :)
<leons>
Does LiteEth by any chance support SGMII interfaces? I don't see it being used in litex-boards anywhere, and there seems to be a PCS implementation, though I'm not sure it applies to Xilinx FPGAs?
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<_florent_>
leons: the pcs_1000basex supports SGMII but not sure I tested it personnaly on a real SGMII interface
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<_florent_>
OmkarBhilare[m]: wishbone-utils should still be working yes, I don't use it that often (litex_server is more convenien for me since I'm familiar with it) but last time I tested wishbone-utils it was working and the protocol hasn't changed since
<_florent_>
david-sawatzke[m: last_be indicates the last valid valid byte in the work, this is only useful for data_width > 8
<_florent_>
BTW, I'll be in vacation for three weeks, so sorry if I'm not very present