ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<krzk>
hey arnd, I found also uncovered by maintainers arm/alphascale and arm/nspire. The nspire is actually TI, so the TI folks should take it to their entry (or add new entry).
<krzk>
arnd: shall I send simialr patch for alphascale like for vt8500?
<arnd>
yes, please do
<arnd>
Regarding nspire, there have been some patches by Andrew Davis from TI, so you could ask him, but as I understand he's in a completely different part of TI that has nothing to do with the calculators, and I think the chips in nspire were done by some other company
<arnd>
krzk: there are a few more obsolete platforms that I ended up not deleting back in 2020 when I asked around for who uses them. It would be nice to have a clearer plan for what we want to do with them in the future
<arnd>
axxia was one that is still used by Nokia at least but is rather incomplete upstream and they never did the promised work on it
<krzk>
arnd: ack. Maybe we should just remove incomplete stuff? One thing is some old, but functional platform like Samsung S3C, other topic is something which no one really knows if it works
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<arnd>
krzk: are you aiming for s3c removal in 6.13 as by the original plan? I'm tempted to drop the non-DT pxa and orion5x at the same time, since nobody has worked on those since we dropped the last set of board files
<bjdooks>
:sadface:
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<krzk>
arnd: I forgot the plan :) but I am fine with 6.13, unless suddenly some user with product pops up
* ukleinek
remembers his zipit in the cupboard that wasn't used in ages
<ukleinek>
(featuring a pxa270 IIRC)
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<arnd>
ukleinek: we removed that in linux-6.3 already, the only pxa board files that are left are gumstix and sharpsl, since those were the most likely to get converted to DT
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<ukleinek>
arnd: ok, so I even missed that.
<arnd>
I left the orion5x machines that were enabled by debian/armel since they seemed to have actual users, but then debian dropped that kernel after determining there are none
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<arnd>
militantorc: you want -march=armv7ve -mfpu=neon-vfpv4 to be the default, but I'm not sure how to pass that to configure
<ardb>
arnd: that assumes LPAE no?
<arnd>
ardb: the compiler doesn't care about LPAE, only the kernel does
<arnd>
armv7ve enables idiva and idivt by default though, unlike armv7-a
<ardb>
fair enough
<ardb>
so armv7ve does not imply atomic 64-bit loads and stores?
<arnd>
not sure, is that something the compiler needs to know about?
<ardb>
it implements atomics no?
<arnd>
the only armv7ve cores in practice are cortex-a7/a15/a17, krait and swift, they should all have that
<arnd>
ardb: what cores have a non-atomic ldrd/strd?
<ardb>
only LPAE guarantees it as far as i know
<ardb>
because of the 64-bit page table descriptors
<arnd>
right, then armv7ve must require it
<ardb>
yeah that is my point
<ardb>
so a compiler targetting armv7ve may avoid calling an intrinsic for 64-bit atomics
<ardb>
and running that code on a non-lpae core may therefore misbehave
<arnd>
I don't think it does that optimization though:
<arnd>
echo 'int f(_Atomic long long *p) { *p = 1; }' | arm-linux-gnueabihf-gcc-12 -march=armv7ve+neon -xc - -S -o- -O2
<arnd>
produces an ldrexd/strexd loop
<ardb>
ok good to know
<ardb>
so that answers my question
<arnd>
it does on read, so something else is going on
<arnd>
echo 'long long f(_Atomic long long *p) { return *p; }' | arm-linux-gnueabihf-gcc-12 -march=armv7ve+neon -xc - -S -o- -O2
<arnd>
this uses ldrd, but with armv7-a it uses ldrexd
<ardb>
ok so that was exactly my point
<ardb>
although i'm not sure i understand what is going on here
<ardb>
is the alignment of long long the same in both cases?
<ardb>
i'd assume so but just checking
<ardb>
iirc eabi made long long 64-bit aligned in all cases
<arnd>
ardb: ok, so I guess the flags above could be a marvell Armada 1500, which I think is the only PJ4B-MP implementation that has both NEON and IDIV but not LPAE
<arnd>
all the other ones that have idiv and neon also have lpae
<arnd>
PJ4C apparently added LPAE according to Documentation/arch/arm/marvell.rst, that is one that I did not remember
<arnd>
OTOH I'm 99% sure that what militantorc is looking at is a regular Cortex-A7, not something unusual ;-)
<arnd>
ardb: yes, eabi assumes natural alignment of all basic types
<ardb>
so why would 'lpae' be missing from their cpuinfo?
<arnd>
oh, I didn't realize that we even report that to userspace
<ardb>
yes it has its own HWCAP
<ardb>
a469abd0f868c902b75532579bf87553dcf1b360
<arnd>
3.10 was a while ago,so it's unlikely to be an old kernel
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<arnd>
militantorc: can you reveal the CPU implementer/architecture/variant/part/revision number or the name of the chip?
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