<cr1901>
charlottia / adamgreig[m] : Noted. I haven't looked at it since yesterday, but I'll rearrange things to see if the issue is fixed
<charlottia>
cr1901: _nodnod_ Failing that, if it works for you, you could pass in `ROM` instead of `ROM()`, and construct it in the body with `m = request.node.get_closest_marker("module").args[0]()`.
<cr1901>
That might be what I end up doing; the intent was to make a pytest plugin eventually to share fixture code (the example is definitely simplified). But need to deploy it a few times before I commit to that
<adamgreig[m]>
I've done a few pytest fixtures for sharing things like this without issue, but I think your problem is specifically instantiating a module (Memory) inside init so it ends up shared, you're basically adding an absolute load of read ports to the same memory if nothing else
<cr1901>
Why don't all the read ports return a value :P?
<adamgreig[m]>
yea, idk, some deeper horror to do with sharing memories between simulators and such I guess
<cr1901>
for a in vars(self): if isinstance(a, Memory): raise cr1901PutAMemoryInInitAgainException
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<cr1901>
charlottia / adamgreig[m] Finally tested this; yes, moving the Memory to elaborate did work. However, seeing as the examples show putting Memory in init (https://github.com/amaranth-lang/amaranth/blob/main/examples/basic/mem.py), I don't know if my original example is "will never be supported" vs "this should be working, but doesn't"
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<charlottia>
Note you could also create the read port in init; then it works, since it means you don't get >1 read port per Memory.
<cr1901>
Actually something's off with my actual code (not public yet)... with the fix supplied as suggested, tests have started passing that should've failed (!!)
<cr1901>
And I know they should've failed b/c I didn't implement the functionality the test tests :D
<charlottia>
This'll include the Memory in elaboration "with" the first read port created for a given Memory.
<charlottia>
But it won't do so for subsequent read ports.
<charlottia>
(Similar done below for write ports iff there are no read ports.)
<cr1901>
oooh, I misread. I see
<charlottia>
This means that, if you then created the 2nd read port for an existing Memory and include that in a design, but not the first, the Memory won't be included.
<charlottia>
So the read port's signals will just sit at reset.
<charlottia>
I think that's the location of your 0s.
<charlottia>
s/location/origin/, s//`/, s//`/
<charlottia>
(since it's in Memory.elaborate that the mem cell is actually created and connections made for all R/W ports of that Memory.)
<cr1901>
Interesting that Memory is also an Elaboratable, but you're not expected to add it as a submodule. So the elaborate calls to submodules will only ever elaborate a Memory if the rd/wr port returns it from its own elaborate()
<cr1901>
Anyways, now gotta figure out why tests for functionality I did not implement are passing. Wheee...
<charlottia>
Indeed! You can in fact Just Add the Memory as the submodule instead, and it'll Just Work. I guess in the second instance it may be trying to power read ports from the older simulation, but prob doesn't matter.
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<cr1901>
Oh. I see. The reason the tests are passing is because I forgot to put in any asserts. That's good.
<cr1901>
That's perfectly fine.
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<sporniket>
Hello, just a little note that I added a post to my series of articles, that is about using pdm and yowasp so that a project is easier to consume for others.