00:45 <_whitenotifier-f> [YoWASP/yosys] whitequark pushed 1 commit to develop-0.34 [+0/-0/±1] https://github.com/YoWASP/yosys/commit/0e77b9106cdd

00:45 <_whitenotifier-f> [YoWASP/yosys] whitequark 0e77b91 - [autorelease] Yosys 0.34.

00:45 <_whitenotifier-f> [yosys] whitequark created branch develop-0.34 - https://github.com/YoWASP/yosys

00:45 <_whitenotifier-f> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/034d20dfb03f...09df83ba66fe

00:45 <_whitenotifier-f> [YoWASP/yosys] whitequark 09df83b - Update dependencies.

01:29 <_whitenotifier-f> [YoWASP/yosys] whitequark created branch release-0.34 https://github.com/YoWASP/yosys/commit/0e77b9106cdd212788463976c73d8fb6bb312ca5

01:29 <_whitenotifier-f> [yosys] whitequark created branch release-0.34 - https://github.com/YoWASP/yosys

01:59 <_whitenotifier-f> [amaranth-soc] jfng opened pull request #55: Migrate elaboratables to lib.wiring components. - https://github.com/amaranth-lang/amaranth-soc/pull/55

07:00 <nates93[m]> wrote a python script to auto-generate latex (using the bytefield package) from `rgb565_layout = data.StructLayout({"red": 5, "green": 6, "blue": 5})`. Only implemented for StructLayout but now that I wrapped my head around things a bit I think the others should be straightforward

07:01 <whitequark[cis]> oh, nice!

07:03 <galibert[m]> The less straightforward part with the other possibilities is going to decide how to represent them :-)

07:03 <galibert[m]> * going to be to decide how

07:04 <whitequark[cis]> holes are straightforward

07:04 <whitequark[cis]> overlaps are multiple rows

07:04 <galibert[m]> (ouch, I'm so not used to lsb-first bit fields representations)

07:04 <galibert[m]> How do overlaps/unions interact with hierarchy?

07:07 <whitequark[cis]> they kind of aren't

07:07 <galibert[m]> Ok, I'm probably missing something, but in {"red": 5, "green": 6, "blue": 5} isn't the order of the fields when you iterate over them undefined?

07:08 <whitequark[cis]> insertion order, so from left to right

07:08 <whitequark[cis]> this changed since python 3.6 and we support 3.8+

07:08 <galibert[m]> I'm reading that dict doesn't have that property and only OrderedDict does?

07:08 <galibert[m]> Ah, python change, good

14:34 <_whitenotifier-f> [amaranth] cr1901 commented on pull request #904: Prototype a new CLI - https://github.com/amaranth-lang/amaranth/pull/904#issuecomment-1750786580

14:54 <_whitenotifier-f> [rfcs] zyp edited pull request #28: Add RFC to allow overriding Value operators - https://github.com/amaranth-lang/rfcs/pull/28

15:08 <_whitenotifier-f> [amaranth] whitequark commented on pull request #904: Prototype a new CLI - https://github.com/amaranth-lang/amaranth/pull/904#issuecomment-1750855904

15:14 <_whitenotifier-f> [amaranth] zyp commented on pull request #929: ast: allow overriding Value operators. - https://github.com/amaranth-lang/amaranth/pull/929#issuecomment-1750870347

16:36 <_whitenotifier-f> [amaranth-lang/amaranth-soc] github-merge-queue[bot] pushed 3 commits to gh-readonly-queue/main/pr-55-a872c1b109b4196893b1d47da27e2f8d9928f4d1 [+0/-0/±20] https://github.com/amaranth-lang/amaranth-soc/compare/e6b4002bee5e^...9ffaf949d853

16:36 <_whitenotifier-f> [amaranth-lang/amaranth-soc] jfng e6b4002 - memory: remove support for address space extension.

16:36 <_whitenotifier-f> [amaranth-lang/amaranth-soc] jfng b11abe2 - wishbone: restrict addr_width to positive integers.

16:36 <_whitenotifier-f> [amaranth-lang/amaranth-soc] jfng 9ffaf94 - Migrate elaboratables to lib.wiring components.

16:36 <_whitenotifier-f> [amaranth-soc] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-55-a872c1b109b4196893b1d47da27e2f8d9928f4d1 - https://github.com/amaranth-lang/amaranth-soc

16:36 <_whitenotifier-f> [amaranth-lang/amaranth-soc] github-merge-queue[bot] pushed 3 commits to main [+0/-0/±20] https://github.com/amaranth-lang/amaranth-soc/compare/a872c1b109b4...9ffaf949d853

16:36 <_whitenotifier-f> [amaranth-lang/amaranth-soc] jfng e6b4002 - memory: remove support for address space extension.

16:36 <_whitenotifier-f> [amaranth-lang/amaranth-soc] jfng b11abe2 - wishbone: restrict addr_width to positive integers.

16:36 <_whitenotifier-f> [amaranth-lang/amaranth-soc] jfng 9ffaf94 - Migrate elaboratables to lib.wiring components.

16:36 <_whitenotifier-f> [amaranth-lang/amaranth-soc] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-55-a872c1b109b4196893b1d47da27e2f8d9928f4d1

16:36 <_whitenotifier-f> [amaranth-soc] jfng closed pull request #55: Migrate elaboratables to lib.wiring components. - https://github.com/amaranth-lang/amaranth-soc/pull/55

16:36 <_whitenotifier-f> [amaranth-soc] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-55-a872c1b109b4196893b1d47da27e2f8d9928f4d1 - https://github.com/amaranth-lang/amaranth-soc

17:03 <jfng[m]> hi! it is time for the weekly SoC meeting; we don't have much on the agenda this week again

17:04 <jfng[m]> amaranth-soc has been fully converted to lib.wiring Components

17:04 <_whitenotifier-f> [rfcs] zyp opened pull request #29: RFC #9: clarify that `.const()` can return a value-castable. - https://github.com/amaranth-lang/rfcs/pull/29

17:04 <jfng[m]> expect some breaking changes, notably w.r.t. memory map assignment, which is now done to wishbone or csr signatures, rather than interfaces

17:06 <cr1901> I'll just read the source when I'm ready to understand how it works