whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
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<jer_emy[m]> is there a way to get amaranth to print all of the log output while building?
<jer_emy[m]> like from yosys, pnr etc
<adamgreig[m]> it's all saved in the build/ file
<adamgreig[m]> so you can check the nextpnr output in build/top.tim etc
<jer_emy[m]> thanks
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<tpw_rules> anybody made any axi stuff yet with streams/interfaces/signatures?
<tpw_rules> also is the StreamSignature here (https://github.com/amaranth-lang/rfcs/blob/main/text/0002-interfaces.md#guide-level-explanation) still the best way to create a custom signature?
<_whitenotifier-f> [amaranth] jeremyherbert opened issue #953: Gowin vendor definitions don't support the GW1NR-LV9QN88PC6/I5 (tang nano 9k) but apicula does - https://github.com/amaranth-lang/amaranth/issues/953
<tpw_rules> cr1901: relevantly i remember you mentioning that you had worked out some of the primitives for the HPS?
<tpw_rules> on cyclone v
<_whitenotifier-f> [amaranth] jeremyherbert commented on issue #953: Gowin vendor definitions don't support the GW1NR-LV9QN88PC6/I5 (tang nano 9k) but apicula does - https://github.com/amaranth-lang/amaranth/issues/953#issuecomment-1811773120
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<galibert[m]> tpw_rules: I'm the cv guy, not cr :-)
<galibert[m]> which one do you need to understand?
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<gruetzkopf> (OT: how similar are sv?)
<_whitenotifier-f> [amaranth] whitequark commented on issue #953: Gowin vendor definitions don't support the GW1NR-LV9QN88PC6/I5 (tang nano 9k) but apicula does - https://github.com/amaranth-lang/amaranth/issues/953#issuecomment-1812418586
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<tpw_rules> galibert[m]: just how the bits work. is it possible to avoid qsys?
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<galibert[m]> What’s qsys, the megafuctions?
<tpw_rules> is there straight up an HPS megafunction? i mean the intel platform designer® specifically
<tpw_rules> i don't see that
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<galibert[m]> Dunno. What I do know it that there is a series of modules for a number of functions
<tpw_rules> how do you use the HPS with quartus
<tpw_rules> i do have a working design i just want to excise the verilog ip junk
<galibert[m]> Which part?
<galibert[m]> There’s like 30 hps interfaces to various stuff
<tpw_rules> qsys casts them all as one entity
<tpw_rules> like you drop a qsys block and it has a bunch of different ports
<galibert[m]> Not-qsys doesn’t
<tpw_rules> i guess what are the necessary ones? i'm only really using the f2h and h2f-lw ports
<tpw_rules> (it also asks a bunch of stuff about sdram config which i never quite understood given that the board boots fine without a bitstream)
<tpw_rules> have you done an hps design before?
<galibert[m]> I often use the dual 32-bits port to test stuff
<tpw_rules> how?
<tpw_rules> ah, the gpio
<tpw_rules> are all the cyclonev_hps_interface_* documented anywhere whether you or altera
<galibert[m]> I actually think they are
<tpw_rules> hm, just throwing the module names into google isn't really turning up much
<tpw_rules> mister seems to have kicked out qsys but the stuff looks like copypasta from it
<galibert[m]> Well you have the names in ip/altera/hps/postfitter_simulation and cv_5v4.pdf describes what they do without ever naming them
<tpw_rules> how does it do the latter?
<tpw_rules> oh i see, the hps simulation chapter
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<_whitenotifier-f> [amaranth] cr1901 opened pull request #954: FlippedInterface should propagate flipped to subinterfaces. - https://github.com/amaranth-lang/amaranth/pull/954
<_whitenotifier-f> [amaranth] codecov[bot] commented on pull request #954: FlippedInterface should propagate flipped to subinterfaces. - https://github.com/amaranth-lang/amaranth/pull/954#issuecomment-1813410714
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<adamgreig[m]> tpw_rules: I have an old migen example of cyclonev_hps_interface_hps2fpga_light_weight + cyclonev_hps_interface_mpu_general_purpose at https://gist.github.com/adamgreig/a19bab78fc279552a29afd7346dffff8 if it's any help
<tpw_rules> so that whole ensemble ran and did what you hoped for?
<tpw_rules> you just needed those two modules?
<tpw_rules> (and quartus didn't whine about placement or whatever)
<adamgreig[m]> yea
<adamgreig[m]> that's everything that was involved and it worked, at least as best as I recall from 6 years ago
<tpw_rules> strange that qsys makes it so damn complicated
<adamgreig[m]> I didn't need both modules, either, I did lots of things with just one or just the other
<tpw_rules> yeah for sure. but like there's not even a clocking module
<adamgreig[m]> I was very glad to discover how simple the cyclonev-soc made talking to the soc actually, but I don't remember ever looking at qsys
<adamgreig[m]> from what I hear of zync it's much more annoying
<adamgreig[m]> in my example the fpga is clocked from a 50MHz clock input
<adamgreig[m]> and the HPS just does whatever it normally does I guess
<_whitenotifier-f> [amaranth] whitequark reviewed pull request #954 commit - https://github.com/amaranth-lang/amaranth/pull/954#discussion_r1394973034
<tpw_rules> yeah
<tpw_rules> there's this specific clocking module in the qsys files that i figured must be at least a minimum
<tpw_rules> there's also all this sdram setup junk
<tpw_rules> which might only exist for simulation. but frankly my goal is to make the comms interfaces simple enough i don't need to simulate them
<tpw_rules> don't want to drag modelsim in either...
<adamgreig[m]> all this junk is what puts me off quartus, and zync entirely, really
<tpw_rules> but i guess if it lets me do it i'll do it
<tpw_rules> would be quite happy to excise qsys and all the verilog in general
<tpw_rules> i do have some zynq boards i bought to play around with
<tpw_rules> (mostly for nixos hegemony)
<tpw_rules> but the cyclone v has actually been rather nice and smooth
<tpw_rules> (ditching qsys also gives up the jtag <-> axi bridges for debugging but i haven't used those so)
<cr1901> whitequark[cis]: How about "elif name in self.__unflipped.signature.members and \self.__unflipped.signature.members[name].is_signature"?
<tpw_rules> is the amaranth-soc CSR stuff ready to bang on?
<_whitenotifier-f> [amaranth] wanda-phi commented on pull request #954: FlippedInterface should propagate flipped to subinterfaces. - https://github.com/amaranth-lang/amaranth/pull/954#issuecomment-1813461883
<Wanda[cis]> oh oops I raced
<cr1901> See my question
<cr1901> I _think_ this is what you're saying to check
<Wanda[cis]> cr1901: yeah that was my suggestion as well
<cr1901> Okay force-pushed
<tpw_rules> (or has anyone set up a demo example?)
<cr1901> Right, actually adding the new changes would help (forgot "-a" to git)
<tpw_rules> ((is it even documented anywhere in any way?))
<Wanda[cis]> cr1901: you may also want to add more tests to this thing, making sure the if branch doesn't fire on too many things
<cr1901> This is all the bandwidth I can muster for tonight, sorry
<cr1901> Thinking about the signature flipping internal stuff hurts my head
<Wanda[cis]> ... yeah, it took me a while to process as well
<Wanda[cis]> (long enough to race with Cat, heh)
<cr1901> I really don't know offhand how to make additional test cases that would be likely to fire the branch. Both clauses of the elif branch are required to prevent existing tests from failing. 1/2
<cr1901> If someone opens an issue that can directly pin blame to #954, I will add more test cases based on that failure, I will have a better idea of additional cases to test
<Wanda[cis]> I'd add a plain member and make sure nothng bad happens to it
<cr1901> where? At the same level as "a" or "b"?
<cr1901> or member as in "not part of the signature at all"?
<Wanda[cis]> at the same as level as "b", otherwise it won't even go through the flip
<Wanda[cis]> a non-member would be nice too