<whitequark[cis]>
Elaboratable is a core concept, wiring.Component is a library concept
<whitequark[cis]>
for the next release we are not mandating wiring.Component (possibly yet)
<whitequark[cis]>
you are free to use either
<tpw_rules>
okay. i just like how this one annotates directions and presumably integrates with verilog.convert better
<whitequark[cis]>
it does in fact integrate with verilog.convert
<tpw_rules>
Component is a part of the new interface stuff too right?
<whitequark[cis]>
yep
<tpw_rules>
okay. i need to get my feet wet wrt that. but i like how i can say In and Out instead of just i_ and o_
<tpw_rules>
i also think it might be more clear to my verilog ultra-newbies
<whitequark[cis]>
yep! sometimes it would be both, like if you have both kinds of ports
<tpw_rules>
what do you mean by kind of port?
<whitequark[cis]>
er, sorry, that's incomprehensible
<whitequark[cis]>
i mean if you have both an in stream and an out stream for example, you'd still use i_ o_ prefixes
<tpw_rules>
ah that's fair
<tpw_rules>
do you mean my statement is incomprehensible?
<whitequark[cis]>
nonono i meant mine was
<whitequark[cis]>
it's late here and i just woke up from a nap, apologies ^^;
<tpw_rules>
that's cool
<tpw_rules>
well i think i'll give Component a spin then. not sure how it relates to interfaces yet but i can try those later. is there a convenient way to render https://github.com/amaranth-lang/amaranth/pull/880/ ?
<crzwdjk>
I appreciate the gradual approach, and also the improvements being made, they make the language that much easier to use for the relatively HDL-clueless such as myself.
<crzwdjk>
As for the relation between Elaboratables and Components, I do have an Elaboratable that is not a Component, because its purpose is to produce the clock and reset signals and thus it has no conventional output signals. Well, at least that's how it works now, maybe one day the clock domain system will be redesigned too.