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<cr1901>
jfng: " Subordinate bus has data width 32, which is not the same as its granularity 8 (required for sparse address translation)" <-- why is this required to get the benefits of incomplete address decoding?
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<jfng[m]>
iirc it has to do with the fact that sparse address translation may never split a bus transaction into multiple ones; in the case of our wishbone primitives, we enforce this by requiring that an interface granularity is the same as its data width i.e. SEL has only one line
<jfng[m]>
<cr1901> "jfng: " Subordinate bus has data..." <- sorry woke up recently so my head is a bit blurry..
<jfng[m]>
for example, our Wishbone to CSR bridge exploits this by having the data width of its CSR bus equal to the granularity of the wishbone bus
<jfng[m]>
btw, no SoC meeting today -- I am taking the day off after a trip to the UK for a Chipflow team meeting
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